Cortex-A8 R2P2.pdf - ARM Information Center

Programmer’s Modela. In Thumb state, access to these registers is limited.2.14.9 Modification of PSR bits by MSR instructionsIn previous architecture versions, MSR instructions can modify the flags byte, bits[31:24], of the CPSR in any mode, but the other three bytes are only modifiable inprivileged modes.After the introduction of ARMv6 however, each CPSR bit falls into one of the followingcategories:• Bits that are freely modifiable from any mode, either directly by MSR instructionsor by other instructions whose side-effects include writing the specific bit orwriting the entire CPSR.Bits in Figure 2-12 on page 2-27 that are in this category are:— N— Z— C— V— Q— GE[3:0]— E.• Bits that must never be modified by an MSR instruction, and so must only be writtenas a side-effect of another instruction. If an MSR instruction does try to modifythese bits the results are architecturally Unpredictable. In the processor these bitsare not affected.Bits in Figure 2-12 on page 2-27 that are in this category are J and T.• Bits that can only be modified from privileged modes, and that are completelyprotected from modification by instructions while the processor is in User mode.The only way that these bits can be modified while the processor is in User modeis by entering a processor exception, as described in Exceptions on page 2-35.Bits in Figure 2-12 on page 2-27 that are in this category are:— A— I— F— M[4:0].ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 2-33