Cortex-A8 R2P2.pdf - ARM Information Center

Clock, Reset, and Power Control• Figure 10-6 on page 10-6 shows that PRESETn must be asserted for a minimumof eight cycles. Because PCLK is an asynchronous clock domain that can operatefaster or slower than CLK, PRESETn must be asserted for the slowest of eightCLK or eight PCLK cycles.The power-on reset also controls entry and exit from a power-down state for variouspower domains within the processor. See Power control on page 10-10 for moreinformation.10.2.2 Soft resetThe soft reset sequence is used to trace with ETM or debug across a reset event. Byasserting only the ARESETn and ARESETNEONn signals, the reset domainscontrolled by nPORESET, ETM, and debug in particular, are not reset. Therefore,breakpoints and watchpoints are retained during a soft reset sequence. Figure 10-7shows a soft reset sequence.REFCLK(PLL input)nPORESETARESETnARESETNEONn8 cycles minimum8 cycles minimumCLKFigure 10-7 Soft reset timingAn additional reset is provided to control the NEON unit independently of the processorreset. This reset can be used to hold the NEON unit in a reset state so that the power tothe NEON unit can be safely removed without placing any logic within the NEON unitin a different state. The reset cycle timing requirements for ARESETNEONn areidentical to those for ARESETn. ARESETNEONn must be held for a minimum ofeight CLK cycles when asserted to guarantee that the NEON unit has entered a resetstate.In addition, both ARESETn and ARESETNEONn are used to manage various powerdomains within the processor. See Power control on page 10-10 for information on themanagement of these resets and power domains.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 10-7