Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorTable 3-123 shows how the bit values correspond with the PLE Channel NumberRegister functions.Table 3-123 PLE Channel Number Register bit functionsBitsFieldFunction[31:1] - Reserved. UNP, SBZ.[0] CN Indicates PLE channel selected:0 = PLE channel 0 selected, reset value1 = PLE channel 1 selected.Access in the Nonsecure state depends on the PLE bit, see c1, Nonsecure AccessControl Register on page 3-73. The processor can access this register in User mode ifthe U bit for any channel is set to 1, see c11, PLE User Accessibility Register onpage 3-139.Table 3-124 shows the results of attempted access for each mode.Table 3-124 Results of access to the PLE User Accessibility Register aSecure privileged Nonsecure privileged Secure User Nonsecure UserUbitPLEbit Read Write Read Write Read Write Read Write0 0 Data Data Undefined Undefined Undefined Undefined Undefined Undefined1 Data Data Data Data Undefined Undefined Undefined Undefined1 0 Data Data Undefined Undefined Data Data Undefined Undefined1 Data Data Data Data Data Data Data Dataa. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessorinstruction is executed.To access the PLE Channel Number Register, read or write CP15 with:MRC p15, 0, , c11, c2, 0 ; Read PLE Channel Number RegisterMCR p15, 0, , c11, c2, 0 ; Write PLE Channel Number Register3-142 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E