Cortex-A8 R2P2.pdf - ARM Information Center

Design for Test11.2 ATPG test featuresThis section describes test features that are included in the RTL to ensure that the DFTimplementation meets minimum requirements:• Wrapper• Enabling sections of the core on page 11-39• Reset handling on page 11-40.• Safe shift RAM signals on page 11-40.11.2.1 WrapperThere are seven input signals that control the logic of the core to support the WrapperBoundary Register (WBR) and the IEEE 1500 standard:• WEXTEST• WINTEST• WSE• CAPTUREWR• TESTMODE• SERIALTEST• SHIFTWR.This logic:• separates the shift and capture for IEEE 1500 compliance so that the sharedwrapper cell can hold state when neither shifting nor capturing• requires only one external wrapper scan enable and prevents unknown states inwrapper cells with multiple capture cycles, which is preferable for delay testingand for testing through the memories.Figure 11-26 on page 11-38 shows the RTL logic for a set of input WBR cells.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 11-37