Cortex-A8 R2P2.pdf - ARM Information Center

Design for TestEach GNG[10:0] field is a concatenation of three fields as Table 11-16 shows.Table 11-16 GNG[10:0] fieldGNG[10:0] bit fieldGNG[10]GNG[9:6]GNG[5:0]Field nameValiddata seed[3:0]pattern selection[5:0]The patterns execute in order, starting with GNG1. It is not necessary to load the entireregister when fewer than eight patterns are required. If you load fewer than eightpatterns, the unloaded fields cannot execute because their valid bits are cleared to 0 atreset.For example, to execute a READBANG with a data seed of 0x6 followed by a COLBARwith a data seed of 0xF, you only have to load two fields:1_0110_101010 → 1_1111_10111 = GNG1[10:0] → GNG2[10:0]See READBANG on page 11-35 and COLBAR on page 11-27 for more details.Figure 11-4 shows the L1 MBIST GO-NOGO Instruction Register contents afterloading a COLBAR with a data seed of 0xF and a READBANG with a data seed of 0x6.In0_xxxx_xxxxxx0_xxxx_xxxxxx1_1111_1011111_0110_1010100_xxxx_xxxxxx0_xxxx_xxxxxx0_xxxx_xxxxxx0_xxxx_xxxxxxFigure 11-4 L1 MBIST GO-NOGO Instruction Register example with two patternsThe MBISTSHIFTL1 signal must toggle one cycle before initiation and one cyclebefore completion of the MBISTDATAINL1 stream as Figure 11-7 on page 11-20shows. During GO-NOGO instruction load, MBISTDSHIFTL1 must toggle at thesame time as MBISTSHIFTL1. See Figure 11-8 on page 11-21.L1 MBIST Datalog RegisterThe L1 MBIST Datalog Register records information about failing arrays. Figure 11-5on page 11-15 shows the fields of the L1 MBIST Datalog Register.11-14 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E