Cortex-A8 R2P2.pdf - ARM Information Center

Design for TestPLL glitchless switch betweenfast and slow clocking occurs hereCLKMBISTRESULT[1] (fail flag)MBISTDSHIFTMBISTRESULT[0] (data log shift out)D[msb–1]D[msb]MBISTRUNFigure 11-12 Timing of MBIST end of bitmap datalog retrieval11.1.4 Pattern selectionThe processor implementation includes a toolbox of patterns for testing the arrays.When creating test vectors, you can select the group of algorithms that is most effectivefor your fabrication process.Some of the pattern sequence descriptions use the following terms:R Read instruction data seed.W Write instruction data seed.R_ Read inverse of instruction data seed.W_ Write inverse of instruction data seed.incr Increment address starting with 0 until address = addrmax.decr Decrement address starting with addrmax until address = 0.wscan Write entire array.rscan Read entire array.N Total number of accesses per address location.11-24 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E