Cortex-A8 R2P2.pdf - ARM Information Center

External Memory Interface9.1 About the external memory interfaceThe external memory interface enables the processor to interface with third levelcaches, peripherals, and external memory. You can configure the processor to connectto either a 64-bit or 128-bit AXI interconnect that provides flexibility to system designs.The external memory interface supports the following interfaces:• read address channel• read data/response channel• write address channel• write data channel• write response channel.All internal requests that require access to an external interface must use the appropriateexternal interface. You can generate requests with the following:• instruction fetch unit• load/store unit• table walk• preload engine• internal L2 cache controller.By using the features of the AXI interconnect that enable split address and datatransactions, in addition to multiple outstanding requests, the processor can reduce theexternal pin interface without reducing performance. The processor has a single AXImaster interface. It does not contain an AXI slave interface.9.1.1 External interface servicing instruction fetch transactionsThe L2 memory system handles all instruction-side cache misses, including those fornoncacheable memory. All instruction fetch requests are read-only and are routed to theexternal read address and data channels. For cacheable memory accesses, a wrappingburst transaction is generated to fetch an entire cache line from external memory. Anonwrapping burst transaction is generated by the L2 memory system for noncacheable,strongly ordered, or device memory instruction fetch accesses. See Table 9-5 onpage 9-7 for information on AXI instruction transactions.9.1.2 External interface servicing data transactionsThe L2 memory system handles all data-side cache misses, including those fornoncacheable memory, and those generated by the preload engine. Read data accessesare routed to the read address and data channels, whereas write data accesses are routed9-2 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E