Cortex-A8 R2P2.pdf - ARM Information Center

Clock, Reset, and Power Control10.1 Clock domainsThe processor has three major clock domains:CLK High speed core clock used to clock all major processor interfaces. TheL1 memory system uses both the rising and falling edges of CLK. If theimplemented design uses logic requiring the negative edge of the CLKsignal, the duty cycle of CLK must be 50%. Figure 10-1 shows this.T PHT PLFigure 10-1 CLK duty cycleCLK controls the following units within the processor:• instruction fetch unit• instruction decode unit• instruction execute unit• load/store unit• L2 cache unit, including AXI interface• NEON unit• ETM unit, not including the ATB interface• debug logic, not including the APB interface.NoteThe instruction fetch, instruction decode, instruction execute, load/store,and L2 cache are called the core or integer core.PCLKATCLKAPB clock that controls the debug interface for the processor. PCLK isasynchronous to CLK and ATCLK. PCLK controls the debug interfaceand logic in the PCLK domain.ATB clock that controls the ATB interface for the processor. ATCLK isasynchronous to CLK and PCLK. ATCLK controls the ATB interface.NoteYou can implement PCLK and ATCLK to be synchronous to CLK. Youcan also implement PCLK and ATCLK to run synchronously to eachother.10.1.1 AXI clocking using ACLKENThe processor contains a single synchronous AXI interface. The AXI interface isclocked using a gated CLK that is gated using ACLKEN. The AXI interface canoperate at any integer multiple slower than the processor clock, CLK. In previous ARM10-2 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E