Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorA translation table base register is selected in the following fashion:• If N is set to 0, always use Translation Table Base Register 0. This is the defaultcase at reset. It is backwards compatible with ARMv5 and earlier processors.• If N is set to a value greater than 0, and bits [31:32-N] of the VA are all zeros, useTranslation Table Base Register 0. Otherwise, use Translation Table BaseRegister 1. N must be in the range 0-7.NoteThe processor cannot perform a translation table walk from L1 cache. Therefore, if C isset to 1, to ensure coherency, you must store translation tables in inner write-throughmemory. If you store the translation tables in an inner write-back memory region, youmust clean the appropriate cache entries after modification so that the mechanism forthe hardware translation table walks sees them.3.2.34 c3, Domain Access Control RegisterThe purpose of the Domain Access Control Register is to hold the access permissionsfor a maximum of 16 domains.The Domain Access Control Register is:• a read/write register banked for Secure and Nonsecure states• accessible in privileged modes only.Figure 3-29 shows the bit arrangement of the Domain Access Control Register.31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0Figure 3-29 Domain Access Control Register formatARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 3-81