Cortex-A8 R2P2.pdf - ARM Information Center

Instruction Cycle Timing16.1 About instruction cycle timingThis chapter provides the information to estimate how much execution time particularcode sequences require. The complexity of the processor makes it impossible toguarantee precise timing information with hand calculations. The timing of aninstruction is often affected by other concurrent instructions, memory system activity,and additional events outside the instruction flow. Describing all possible instructioninteractions and all possible events taking place in the processor is beyond the scope ofthis document. Only a cycle-accurate model of the processor can produce precisetimings for a particular instruction sequence.This chapter provides a framework for doing basic timing estimations for instructionsequences. The framework requires three main information components:Instruction-specific scheduling informationThis includes the number of micro-operations for each main instructionand the source and destination requirements for each micro-operation.The processor can issue a series of micro-operations to the executionpipeline for each ARM instruction executed. Most ARM instructionsexecute only one micro-operation. More complex ARM instructions suchas load multiples can consist of several micro-operations.Dual issue restriction criteriaThis is the set of rules used to govern which instruction types can dualissue and under what conditions. This information is provided for dualissue of ARM instructions and Advanced SIMD instructions.Other pipeline-dependent latenciesIn addition to the time taken for the scheduling and issuing ofinstructions, there are other sources of latencies that effect the time of aprogram sequence. The two most common examples are a branchmispredict and a memory system stall such as a data cache miss of a loadinstruction. These cases are the most difficult to predict and often mustbe ignored or estimated using statistical analysis techniques. Fortunately,you can ignore most of these additional latencies when creating anoptimal hand scheduling for a code sequence. Hand scheduling is themost useful application of this cycle timing information.16-2 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E