Cortex-A8 R2P2.pdf - ARM Information Center

System Control Coprocessora. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessorinstruction is executed.b. The EN bit in c9, User Enable Register on page 3-117 enables User mode access of the Performance Monitor Registers.To access the EVTSEL Register, read or write CP15 with:MRC p15, 0, , c9, c13, 1 ; Read EVTSEL RegisterMCR p15, 0, , c9, c13, 1 ; Write EVTSEL RegisterTable 3-97 shows the range values for predefined events that you can monitor using theEVTSEL Register.Table 3-97 Values for predefined eventsValueDescription0x00 Software increment. The register is incremented only on writes to the Software Increment Register. See c9,Software Increment Register on page 3-107.0x010x020x030x04Instruction fetch that causes a refill at the lowest level of instruction or unified cache. Each instruction fetchfrom normal cacheable memory that causes a refill from outside of the cache is counted. Accesses that donot cause a new cache refill, but are satisfied from refilling data of a previous miss are not counted. Whereinstruction fetches consist of multiple instructions, these accesses count as single events. CP15 cachemaintenance operations do not count as events. This counter increments for speculative instruction fetchesand for fetches of instructions that reach execution.Instruction fetch that causes a TLB refill at the lowest level of TLB. Each instruction fetch that causes atranslation table walk or an access to another level of TLB caching is counted. CP15 TLB maintenanceoperations do not count as events. This counter increments for speculative instruction fetches and for fetchesof instructions that reach execution.Data read or write operation that causes a refill at the lowest level of data or unified cache. Each data readfrom or write to normal cacheable memory that causes a refill from outside of the cache is counted. Accessesthat do not cause a new cache refill, but are satisfied from refilling data of a previous miss are not counted.Each access to a cache line to normal cacheable memory that causes a new linefill is counted, including themultiple transaction of instructions such as LDM or STM, PUSH and POP. Write-through writes that hit inthe cache do not cause a linefill and so are not counted. CP15 cache maintenance operations do not count asevents. This counter increments for speculative data accesses and for data accesses that are explicitly madeby instructions.Data read or write operation that causes a cache access at the lowest level of data or unified cache. Eachaccess to a cache line to normal cacheable memory is counted including the multiple transaction ofinstructions such as LDM or STM. CP15 cache maintenance operations do not count as events. This counterincrements for speculative data accesses and for data accesses that are explicitly made by instructions.3-112 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E