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AC CharacteristicsTable 17-4 Timing parameters of APB interface and miscellaneous debug signals (continued)Signal Clock Setup parameterPercent ofclock periodHold parameterPADDR31 PCLK T ispaddr31 30% T ihpaddr31PADDR11TO2[11:2] PCLK T ispaddr11to2 30% T ihpaddr11to2PENABLE PCLK T ispenable 30% T ihpenablePSELCTI e PCLK T ispselcti 30% T ihpselctiPSELDBG PCLK T ispseldbg 30% T ihpseldbgPSELETM d PCLK T ispseletm 30% T ihpseletmPWRITE PCLK T ispwrite 30% T ihpwritePRDATA[31:0] PCLK T ovprdata 30% T ohprdataPWDATA[31:0] PCLK T ispwdata 30% T ihpwdataPREADY PCLK T ovpready 30% T ohpreadyPSLVERR PCLK T ovpslverr 30% T ohpslverrNIDEN a PCLK - - -SPIDEN a PCLK - - -SPNIDEN a PCLK - - -a. This signal has multiple end-points and must be treated as level-sensitive.b. This is a static input to the processor.c. This signal is not required because debug and the ETM use the same power domain.d. Figure 10-6 on page 10-6 shows how this signal must be set up.e. This signal is not present when the processor is configured without the ETM.17-8 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E
AC Characteristics17.5 L1 and L2 MBIST interfacesTable 17-5 shows the setup and hold times for the L1 and L2 interfacesTable 17-5 Timing parameters of the L1 and L2 MBIST interfaceSignalClockSetupparameterPercent ofclock periodHoldparameterMBISTDATAINL1 CLK T ismbistdatainl1 30% T ihmbistdatainl1MBISTDSHIFTL1 CLK T ismbistdshiftl1 30% T ihmbistdshiftl1MBISTMODEL1 CLK T ismbistmodel1 30% T ihmbistmodel1MBISTRUNL1 CLK T ismbistrunl1 30% T ihmbistrunl1MBISTSHIFTL1 CLK T ismbistshiftl1 30% T ihmbistshiftl1MBISTRESULTL1[2:0] CLK T ovmbistresultl1 30% T ihmbistresultl1MBISTDATAINL2 CLK T ismbistdatainl2 30% T ihmbistdatainl2MBISTDSHIFTL2 CLK T ismbistdshiftl2 30% T ihmbistdshiftl2MBISTMODEL2 CLK T ismbistmodel2 30% T ihmbistmodel2MBISTRUNL2 CLK T ismbistrunl2 30% T ihmbistrunl2MBISTSHIFTL2 CLK T ismbistshiftl2 30% T ihmbistshiftl2MBISTRESULTL2[2:0] CLK T ovmbistresultl2 30% T ohmbistresultl2MBISTUSERINL2[18:0] CLK T ismbistuserinl2 30% T ihmbistuserinl2MBISTUSEROUTL2[4:0] CLK T ovmbistuseroutl2 50% T ohmbistuseroutl2ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 17-9
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Cortex -A8Revision: r2p2Technical R
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Product StatusThe information in th
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ContentsCortex-A8 Technical Referen
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Contents7.8 Parity detection ......
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ContentsA.2 ATB interface .........
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List of TablesCortex-A8 Technical R
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List of TablesTable 3-103 Results o
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List of TablesTable 12-1 Access to
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List of TablesTable 15-3 CTI regist
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List of Tablesxx Copyright © 2006-
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List of FiguresFigure 3-10 Memory M
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List of FiguresFigure 10-13 Retenti
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List of FiguresFigure 15-16 CTI Cha
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PrefaceAbout this manualThis is the
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PrefaceChapter 16 Instruction Cycle
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PrefacePrefix CPrefix HPrefix nPref
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PrefaceFeedbackARM welcomes feedbac
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Introduction1.1 About the processor
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Introduction1.3 Components of the p
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Introduction1.3.4 Load/storeThe loa
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Introduction1.4 External interfaces
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Introduction1.6 Power managementThe
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Introduction1.8 Product revisionsTh
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Introduction1-14 Copyright © 2006-
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Programmer’s Model• Hardware co
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Programmer’s Model2.2 Thumb-2 ins
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Programmer’s Model2.3 ThumbEE ins
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Programmer’s ModelThumbEE Handler
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Programmer’s Model2.4 Jazelle Ext
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Programmer’s Model— the registe
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Programmer’s ModelNonsecureSecure
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Programmer’s Model2.7 VFPv3 archi
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Programmer’s Model2.9 Data typesT
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Programmer’s ModelBitHigher addre
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Programmer’s Model2.12 Operating
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Programmer’s ModelIn privileged m
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Programmer’s Model16 generalpurpo
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Programmer’s ModelIn ARM state, y
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Programmer’s Model2.14.5 The GE[3
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Programmer’s ModelT bitThe T bit
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Programmer’s ModelOnly secure pri
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Programmer’s Model2.15.2 Leaving
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Programmer’s ModelAn internal or
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Programmer’s ModelImprecise data
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Programmer’s ModelNoteIf the Embe
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Programmer’s Model2.16 Software c
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Programmer’s Model2.17.2 Security
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Programmer’s Model2.18 Control co
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System Control Coprocessor3.1 About
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System Control CoprocessorTable 3-1
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System Control CoprocessorSecurity
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System Control Coprocessor3.1.6 Sys
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System Control CoprocessorThe TCM T
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System Control CoprocessorFigure 3-
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System Control Coprocessor31 28 27
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System Control Coprocessor3.2.20 c0
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System Control Coprocessora. An ent
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System Control CoprocessorThe Auxil
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System Control CoprocessorBits Fiel
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System Control Coprocessora. n is t
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System Control CoprocessorMRC p15,
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System Control CoprocessorVA to PA
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System Control CoprocessorInvalidat
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System Control CoprocessorThe PMNC
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System Control CoprocessorCWhen wri
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System Control Coprocessorb. The EN
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System Control CoprocessorCWhen rea
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System Control Coprocessor• acces
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System Control CoprocessorYou can c
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System Control CoprocessorIf the op
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System Control CoprocessorTo access
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System Control Coprocessora. An ent
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System Control CoprocessorTo access
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System Control CoprocessorThe PLE I
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System Control CoprocessorTo perfor
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System Control CoprocessorLDR R1, =
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System Control CoprocessorLDR R1, =
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System Control CoprocessorL1 Data 0
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System Control CoprocessorInstructi
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System Control CoprocessorParity/EC
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System Control CoprocessorL2 parity
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System Control CoprocessorThe L2 da
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Chapter 4Unaligned Data and Mixed-e
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Unaligned Data and Mixed-endian Dat
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Unaligned Data and Mixed-endian Dat
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Chapter 5Program Flow PredictionThi
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Program Flow Prediction5.2 Predicte
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Program Flow Prediction5.2.1 Return
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Program Flow Prediction5.4 Guidelin
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Program Flow Prediction5.6 Operatin
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Chapter 6Memory Management UnitThis
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Memory Management Unit6.2 Memory ac
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Memory Management Unit6.4 MMU inter
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Memory Management Unit6.6 TLB lockd
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Chapter 7Level 1 Memory SystemThis
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Level 1 Memory System7.2 Cache orga
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Level 1 Memory System7.3 Memory att
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Level 1 Memory SystemTable 7-1 Memo
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Level 1 Memory System7.5 Data cache
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Level 1 Memory SystemAn exception t
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Level 1 Memory System7.8 Parity det
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Chapter 8Level 2 Memory SystemThis
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Level 2 Memory System8.2 Cache orga
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Level 2 Memory System8.3 Enabling a
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Level 2 Memory SystemControl Regist
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Level 2 Memory System8.4.4 Memory r
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Level 2 Memory System8.5 Synchroniz
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Level 2 Memory System8.6 Locked acc
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Chapter 9External Memory InterfaceT
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External Memory Interfaceto the wri
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External Memory InterfaceTable 9-2
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External Memory Interface9.3 AXI in
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External Memory InterfaceBWBCNoTTSS
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Chapter 10Clock, Reset, and Power C
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Clock, Reset, and Power Controlfami
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Clock, Reset, and Power Control10.2
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Clock, Reset, and Power Control•
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Clock, Reset, and Power Control2. F
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Clock, Reset, and Power ControlNote
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Clock, Reset, and Power ControlAfte
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Clock, Reset, and Power Control•
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Clock, Reset, and Power Control—
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Clock, Reset, and Power ControlThe
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Clock, Reset, and Power ControlPowe
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Clock, Reset, and Power ControlTo p
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Clock, Reset, and Power ControlPowe
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Clock, Reset, and Power ControlATBI
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Clock, Reset, and Power Control7. P
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Chapter 11Design for TestThis chapt
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Design for Test11.1.2 MBIST registe
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Design for Testdseed[3:0]Write the
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Design for TestNoteOnly arrays with
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Design for Test• read and write l
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Design for TestTable 11-10 Selectin
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Design for TestTable 11-15 shows ho
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Design for TestArrayFail[22:0] fail
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Design for TestWhen testing the tag
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Design for Test• Bitmap test mode
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Design for TestCLKARESETnMBISTMODEM
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Design for TestCLKARESETnMBISTMODEM
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Design for TestTable 11-19 shows th
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Design for TestNoteNormal MBIST tes
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Design for TestRowmaxmax - 11 1 1 1
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Design for Test2. R, W_, R_, incr.3
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Design for TestRow3210Addressingdir
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Design for TestRow32100 00 00 00 00
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Design for Test11.2 ATPG test featu
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Design for TestWBR in place of the
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Design for TestOne methodology for
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Chapter 12DebugThis chapter describ
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Debug12.1.3 Debug targetThe debug t
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DebugWhen execution of a monitor ta
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Debug12.3 Debug register interfaceY
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DebugTable 12-3 Debug memory-mapped
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Debug12.3.6 Power domains and debug
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DebugLocks permissionYou can lock t
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DebugTable 12-6 shows the behavior
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Debug12.4 Debug register descriptio
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DebugTable 12-11 shows how the bit
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DebugThe Debug Self Address Offset
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DebugBits Field FunctionTable 12-14
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DebugBits Field Function[9] - Reser
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DebugThe DTR access mode can be one
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DebugBitsFieldFunctionTable 12-16 s
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DebugTable 12-17 Vector Catch Regis
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Debug31 3 2 1 0ReservedNot write-th
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DebugTable 12-23 Breakpoint Control
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Debug12.4.16 Watchpoint Control Reg
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DebugTable 12-26 Watchpoint Control
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DebugNoteOn system reset, PRSR[1] r
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DebugTable 12-32 Management registe
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DebugFigure 12-19 shows the bit arr
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Debug12.5.5 Integration Mode Contro
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Debug12.5.8 Lock Access RegisterThe
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Debug31 8 7 6 5 4 3 2 1 0ReservedSe
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DebugTable 12-44 Peripheral Identif
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DebugTable 12-50 shows how the bit
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Debug12.6.2 Halting debug event•
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Debug12.6.5 Watchpoint debug events
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DebugNoteThe Data Abort handler che
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DebugIf the debugged code is not ru
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DebugTable 12-54 shows the read PC
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Debug12.8.4 Writing to the CPSR in
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DebugCoprocessor instructionsThe ru
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DebugSVCSMCUndefinedThe processor i
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Debug12.9 Cache debugThere are seve
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Debug12.10 External debug interface
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DebugDBGROMADDRThe DBGROMADDR signa
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Debug4. Issue an Instruction Synchr
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Debug12.11.1 Debug communications c
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DebugDebugger access to the DCCA de
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DebugTable 12-58 Values to write to
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Debug}when 1:byte_address_select :=
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DebugNoteIn Example 12-10 on page 1
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Debug12.11.5 Debug state exitWhen e
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DebugExample 12-15 Reading the PCRe
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DebugExample 12-19 Checking for an
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DebugExample 12-22 shows the sequen
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Debug}dscr := ReadDebugRegister(34)
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Debug}scr := (scr | 1);WriteCPReg(1
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DebugIf on a power-down request fro
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Debug; Step 2. Loop writing words f
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Chapter 13NEON and VFP Programmer
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NEON and VFP Programmer’s Modelre
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NEON and VFP Programmer’s ModelS0
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NEON and VFP Programmer’s ModelBa
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NEON and VFP Programmer’s ModelFC
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NEON and VFP Programmer’s ModelTa
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NEON and VFP Programmer’s Model31
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NEON and VFP Programmer’s ModelCo
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Chapter 14Embedded Trace MacrocellT
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Embedded Trace Macrocell14.1.2 The
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Embedded Trace Macrocell(DAP) throu
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Embedded Trace MacrocellTable 14-1
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Embedded Trace MacrocellRegister na
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Embedded Trace MacrocellSee the ETM
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Embedded Trace Macrocell14.5 Precis
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Embedded Trace MacrocellThe followi
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Embedded Trace Macrocellcomparator
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Embedded Trace Macrocell14.8 Instru
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Embedded Trace MacrocellWhen a WFI
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Embedded Trace MacrocellYou can use
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Chapter 15Cross Trigger InterfaceTh
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Cross Trigger Interface• An input
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Cross Trigger Interface15.1.2 The c
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Cross Trigger InterfaceTable 15-2 T
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Cross Trigger Interface15.4 About t
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Cross Trigger InterfaceTable 15-3 C
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Cross Trigger Interface15.6 CTI reg
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Cross Trigger InterfaceNoteThe CTII
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Cross Trigger InterfaceBits Field F
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Cross Trigger Interface15.6.9 CTI T
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Cross Trigger InterfaceTable 15-14
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Cross Trigger Interface15.7.4 ITTRI
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Cross Trigger Interface15.8.3 Devic
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Cross Trigger InterfaceActual Compo
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Chapter 16Instruction Cycle TimingT
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Page 685 and 686: Instruction Cycle Timing16.7.2 VFP
Page 687 and 688: Chapter 17AC CharacteristicsThis ch
Page 689 and 690: AC CharacteristicsThe timing parame
Page 691 and 692: AC CharacteristicsTable 17-2 Timing
Page 693: AC Characteristics17.4 APB interfac
Page 697 and 698: AC Characteristics17.7 DFT interfac
Page 699 and 700: AC Characteristicsb. Figure 10-6 on
Page 701 and 702: Appendix ASignal DescriptionsThis a
Page 703 and 704: Signal DescriptionsA.2 ATB interfac
Page 705 and 706: Signal DescriptionsTable A-3 MBIST
Page 707 and 708: Signal DescriptionsA.4 Preload engi
Page 709 and 710: Signal DescriptionsTable A-6 APB in
Page 711 and 712: Signal DescriptionsTable A-7 Miscel
Page 717 and 718: Signal DescriptionsA.8 Miscellaneou
Page 719 and 720: Appendix BInstruction MnemonicsThis
Page 721 and 722: Instruction MnemonicsTable B-1 Adva
Page 723 and 724: Instruction MnemonicsB.2 VFP data-p
Page 725 and 726: GlossaryThis glossary describes som
Page 727 and 728: GlossaryApplication Specific Integr
Page 729 and 730: GlossaryRead ID capabilityThe maxim
Page 731 and 732: GlossaryByte-invariantIn a byte-inv
Page 733 and 734: GlossaryCAM includes comparison log
Page 735 and 736: GlossaryDouble-precision valueConsi
Page 737 and 738: Glossary• arithmetic operation re
Page 739 and 740: GlossaryInvalidateJazelle architect
Page 741 and 742: GlossaryPAPenaltyPower-on resetPref
Page 743 and 744: GlossarySetSet-associative cacheSee
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GlossaryTrapTrigger instructionAn e
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GlossaryWrite-back (WB)Write buffer
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