Cortex-A8 R2P2.pdf - ARM Information Center

DebugBits Field FunctionTable 12-14 Debug Status and Control Register bit functions (continued)[5:2] Entry Method of entry bits. This is a read/write field.b0000 = a DRCR[0] halting debug event occurred, reset valueb0001 = a breakpoint occurredb0100 = an EDBGRQ halting debug event occurredb0011 = a BKPT instruction occurredb0101 = a vector catch occurredb1000 = an OS unlock catch occurredb1010 = a precise watchpoint occurredother = reserved.These bits are set to indicate any of:• the cause of a debug exception• the cause for entering debug state.A Prefetch Abort or Data Abort handler must check the value of the CP15 Fault StatusRegister to determine whether a debug exception occurred and then use these bits todetermine the specific debug event.[1] a Core restarted Core restarted bit:0 = The processor is exiting debug state.1 = The processor has exited debug state. This is the reset value.The debugger can poll this bit to determine when the processor responds to a request to leavedebug state.[0] a Core halted Core halted bit:0 = The processor is in normal state. This is the reset value.1 = The processor is in debug state.The debugger can poll this bit to determine when the processor has entered debug state.a. These bits always reflect the status of the processor and, therefore they return to their reset values if the particular reset eventaffects the processor. For example, a PRESETn event leaves these bits unchanged whereas a core reset event such asnPORESET or ARESETn sets DSCR[18] to a 0 and DSCR[1:0] to b10.To access the Debug Status and Control Register, read CP14 c1 with:MRC p14, 0, , c0, c1, 0 ; Read Debug Status and Control RegisterDTR access modeYou can use the DTR access mode field to optimize data transfer between a debuggerand the processor.12-28 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E