Cortex-A8 R2P2.pdf - ARM Information Center

System Control Coprocessor3.2.58 c10, Memory Region Remap RegistersThe purpose of the Memory Region Remap Registers is to remap memory regionattributes encoded by the TEX[2:0], C, and B bits in the translation tables that the dataside, instruction side, and PLE use. See MMU software-accessible registers on page 6-8for information on memory remap.The Memory Region Remap Registers are:• two read/write registers banked for the Secure and Nonsecure states:— the Primary Region Remap Register— the Normal Memory Remap Register.• accessible in privileged modes only.These registers apply to all memory accesses and this includes accesses from the dataside, instruction side, and PLE. Table 3-113 on page 3-133 shows the purposes of theindividual bits in the Primary Region Remap Register. Table 3-115 on page 3-135shows the purposes of the individual bits in the Normal Memory Remap Register.NoteThe behavior of the Memory Region Remap Registers depends on the TEX Remap bit,see c1, Control Register on page 3-58.Table 3-112 describes the behavior of memory accesses when the region remappedregisters, PRRR and NMRR, are applied.Table 3-112 Application of remapped registers on memory accessCP15 M bit CP15 TRE bit Expected behavior0 0 Memory accesses are controlled by the remapped defaultmemory attributes as defined in the ARM ArchitectureReference Manual0 1 Memory accesses are not remapped but used the defaultmemory attributes1 0 Memory accesses are not remapped and are controlled bythe MMU translation table descriptors1 1 Memory accesses are controlled by the remapped MMUtranslation table descriptorsFigure 3-51 on page 3-133 shows the bit arrangement of the Primary Region RemapRegister.3-132 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E