Cortex-A8 R2P2.pdf - ARM Information Center

Design for Test• read and write latency of the L2 tag array• number of rows of the L2 data, parity, tag and valid physical RAM• testing of valid RAM separately or in parallel with tag RAM testing• column address LSB sequencing of 00, 01, 10, 11 or 00, 01, 11, 10.Table 11-7 shows the bit fields of L2_config[22:0].Table 11-7 L2_config[22:0]L2_config bit fieldL2_config[22:19]L2_config[18:17]L2_config[16:5]L2_config[4]L2_config[3:0]Field nameL2DLat[3:0]L2TLat[1:0]L2Rows[11:0]L2ValSerL2AdLSB[3:0]L2DLat[3:0]Use the L2DLat[3:0] field to select the read and write latency of the L2 data array asTable 11-8 shows. The reset value of the L2DLat[3:0] field is b1111.Table 11-8 Selecting L2 data array latency with L2DLat[3:0]L2DLat[3:0]Wait statesb0000 2b0001 2b0010 3b0011 4b0100 5b0101 6b0110 7b0111 8b1000 9b1001 10ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 11-9