Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorYou can perform these operations on either:• instruction TLB• data TLB.To perform TLB operations, write CP15 with:MCR p15, 0, , c8, c5, 0 ; Invalidate Inst-TLBMCR p15, 0, , c8, c5, 1 ; Invalidate Inst-TLB entry (MVA)MCR p15, 0, , c8, c5, 2 ; Invalidate Inst-TLB (ASID)MCR p15, 0, , c8, c6, 0 ; Invalidate Data-TLBMCR p15, 0, , c8, c6, 1 ; Invalidate Data-TLB entry (MVA)MCR p15, 0, , c8, c6, 2 ; Invalidate Data-TLB (ASID)MCR p15, 0, , c8, c7, 0 ; Invalidate Inst-TLB and Data-TLBMCR p15, 0, , c8, c7, 1 ; Invalidate Inst-TLB and Data-TLB entry (MVA)MCR p15, 0, , c8, c7, 2 ; Invalidate Inst-TLB and Data-TLB (ASID)All other ARMv7-A TLB maintenance encodings are Unpredictable.Functions that update the contents of the TLB occur in program order. Therefore, anexplicit data access before the TLB function uses the old TLB contents, and an explicitdata access after the TLB function uses the new TLB contents. For instruction accesses,TLB updates are guaranteed to have taken effect before the next pipeline flush. Thisincludes flush prefetch buffer operations and exception return sequences.Invalidate TLB unlocked entriesInvalidate TLB unlocked entries invalidates all the unlocked entries in the TLB.Invalidate TLB Entry by MVAFor an area of memory to be remapped, you can use the Invalidate TLB Entry by MVAto invalidate any TLB entry, locked or unlocked, by either:• matching the MVA and ASID• matching the MVA for a globally marked TLB entry.The operation uses both the MVA and ASID as arguments. Figure 3-36 shows theformat.31 12 11 8 70Modified virtual addressReservedASIDFigure 3-36 TLB Operations MVA and ASID format3-100 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E