Cortex-A8 R2P2.pdf - ARM Information Center

Instruction Cycle Timing16.7 VFP instructionsAll VFP data-processing instructions can execute on the VFP coprocessor. A specialsubset of the VFP instructions can execute on the NEON Floating-Point (NFP) pipeline.NoteThis document uses the older assembler language instruction mnemonics. SeeAppendix B Instruction Mnemonics for information about the Unified AssemblerLanguage (UAL) equivalents of the VFP data-processing instruction mnemonics. Seethe ARM Architecture Reference Manual for more information on the UAL syntax.16.7.1 VFP instruction execution in the VFP coprocessorThe VFP coprocessor is a nonpipelined floating-point execution engine that can executeany VFPv3 data-processing instruction. Each instruction runs to completion before thenext instruction can issue, and there is no forwarding of VFP results to otherinstructions. Two cycles of decode, stages M2 and M3, are required betweenconsecutive VFP instructions. These decode cycles are included in the cycle timing ofthis section.The number of cycles required to complete an instruction depends on both theinstruction and the input data operands. Floating-point operands can be divided intothree broad categories:• normal• subnormal• special.Most numbers are normal and have an internal format that consists of a sign, a fractionalnumber between one and two, and an exponent. Subnormal numbers are too small torepresent in the normal space. A subnormal number consists of a sign, a fractionalnumber between zero and one, and a zero in the exponent field. Special numbers arezeros, NaNs, and infinities.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 16-41