Cortex-A8 R2P2.pdf - ARM Information Center

List of TablesCortex-A8 Technical Reference ManualChange History ............................................................................................................. iiTable 1-1 Cortex-A8 configurable options ............................................................................... 1-11Table 2-1 ThumbEE Configuration Register bit functions ......................................................... 2-7Table 2-2 ThumbEE HandlerBase Register bit functions .......................................................... 2-8Table 2-3 Access to ThumbEE registers ................................................................................... 2-9Table 2-4 Jazelle Identity Register bit functions ...................................................................... 2-10Table 2-5 Jazelle Main Configuration Register bit functions ................................................... 2-11Table 2-6 Jazelle OS Control Register bit functions ................................................................ 2-12Table 2-7 Address types in the processor system .................................................................. 2-21Table 2-8 Mode structure ........................................................................................................ 2-22Table 2-9 Register mode identifiers ........................................................................................ 2-24Table 2-10 GE[3:0] settings ....................................................................................................... 2-30Table 2-11 PSR mode bit values ............................................................................................... 2-32Table 2-12 Exception entry and exit .......................................................................................... 2-35Table 2-13 Exception priorities .................................................................................................. 2-42Table 3-1 System control coprocessor register functions ......................................................... 3-3Table 3-2 CP15 registers affected by CP15SDISABLE ............................................................ 3-6Table 3-3 Summary of CP15 registers and operations ............................................................. 3-9Table 3-4 Main ID Register bit functions ................................................................................. 3-25Table 3-5 Results of access to the Main ID Register .............................................................. 3-26Table 3-6 Cache Type Register bit functions .......................................................................... 3-27Table 3-7 Results of access to the Cache Type Register ....................................................... 3-27Table 3-8 Results of access to the TCM Type Register .......................................................... 3-28ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. xi