Cortex-A8 R2P2.pdf - ARM Information Center

Programmer’s ModelAn internal or external abort is either:• a prefetch abort• a data abort.In addition, aborts can be precise or imprecise. A precise abort occurs on the instructionassociated with the access that triggers the abort exception. An imprecise abort canoccur on an instruction subsequent to the instruction associated with the access thattriggers the abort exception.NoteAll aborts from the TLB are internal except for aborts from translation table walks thatare external precise aborts. If the EA bit is 1 for translation aborts, the core branches toMonitor mode in the same way as it does for all other external aborts. See c1, SecureConfiguration Register on page 3-69.IRQs are disabled when an abort occurs. When the aborts are configured to branch toMonitor mode, the FIQ is also disabled.Prefetch abortA prefetch abort is associated with an instruction fetch as opposed to a data access.When a prefetch abort occurs, the processor marks the prefetched instruction as invalid,but does not take the exception until it executes the instruction. If the processor does notexecute the instruction, for example because a branch occurs while it is in the pipeline,the abort does not take place.After dealing with the cause of the abort, the handler executes the following instructionirrespective of the processor operating state:SUBS PC,R14_abt,#4This action restores both the PC and the CPSR, and retries the aborted instruction.Data abortA data abort is associated with a data access as opposed to an instruction fetch.Data aborts on the processor can be precise or imprecise.Internal precise data aborts are those generated by data load or store accesses that theMMU checks:• alignment faults• translation faults2-38 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E