Cortex-A8 R2P2.pdf - ARM Information Center

AC Characteristics17.1 About setup and hold timesThe setup and hold times of processor interface signals are necessary timing parametersfor analyzing processor performance. This chapter specifies the setup and hold times ofthe processor interface signals.The notation for setup and hold times of input signals is:T is Input setup time. T is is the amount of time the input data is valid beforethe next rising clock edge.T ih Input hold time. T ih is the amount of time the input data is valid after thenext rising clock edge.Figure 17-1 shows the setup and hold times of an input signal.CLKINPUT SIGNALinput dataT issignalT ihsignalFigure 17-1 Input timing parametersThe time during which the processor can sample input data is Tissignal.The notation for setup and hold times of output signals is:T ov Output valid time. T ov is the amount of time after the rising clock edgebefore valid output data appears.T oh Output hold time. T oh is the amount of time the output data is valid afterthe next rising clock edge.Figure 17-2 shows the setup and hold times of an output signal.CLKOUTPUT SIGNALoutput dataT ovsignalT ohsignalFigure 17-2 Output timing parameters17-2 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E