Cortex-A8 R2P2.pdf - ARM Information Center

Debug31 3 2 1 0ReservedSticky reset statusReset statusSticky power-down statusPower-down statusBits Field FunctionFigure 12-18 PRSR formatTable 12-31 shows how the bit values correspond with the PRSR functions.[31:4] - Reserved. RAZ, SBZP.Table 12-31 PRSR bit functions[3] Sticky reset status Sticky reset status bit. This bit is cleared to 0 on read:0 = the processor has not been reset since the last time this register was read1 = the processor has been reset since the last time this register was read.This sticky bit is set to 1 when either ARESETn or nPORESET is asserted.This sticky bit is set to 0 when PRESETn is asserted.If both PRESETn and ARESETn or nPORESET are asserted at the same time,this bit is set to an Unpredictable value.[2] Reset status Reset status bit:0 = the processor is not currently held in reset1 = the processor is currently held in reset.This bit reads 1 when either ARESETn or nPORESET is asserted.[1] Sticky power-down status Sticky power-down status bit. This bit is cleared to 0 on read:0 = the processor has not powered down since the last time this register was read1 = the processor has powered down since the last time this register was read. Thisis the reset value.[0] Power-down status Power-down status bit. This status bit reflects the invert value of theDBGPWRDWNREQ input:0 = the core is not powered up1 = the core is powered up.12-52 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E