Cortex-A8 R2P2.pdf - ARM Information Center

DebugThe debugger can maintain cache coherency in both these situations with the followingfeatures:• If bit [2] of the DSCCR is set to 0 while the processor is in debug state, it treatsany memory access that hits in either L1 data cache or L2 cache as write-through,regardless of the memory region attributes. This guarantees that the L1 instructioncache can see the changes to the code region without the debugger executing atime-consuming and device-specific sequence of cache clean operations.• After the code is written to memory, the debugger can execute either a CP15I-cache Invalidate All or a CP15 I-cache Invalidate Line by MVA operation.Note• The processor can execute CP15 I-cache Invalidate All or CP15 I-cache InvalidateLine by MVA operation only in privileged mode. However, in debug state theprocessor can execute these instructions even when invasive debug is notpermitted in privileged mode. This exception to the CP15 permission rulesdescribed in Coprocessor instructions on page 12-83 enables the debugger tomaintain coherency in a secure user debug scenario.• The CP15 Flush Branch Target Buffer instruction is also valid in debug stateregardless of the processor mode. Although the processor implements thisinstruction as a NOP, making it available in debug state ensures softwarecompatibility with other ARMv7 compliant processors.• Execution of the CP15 I-cache Invalidate All operation while in nonsecure stateflushes the secure and nonsecure lines from the I-cache.• If bit [2] of the DSCCR is set to 0 while the processor is in debug state, thenmemory writes go through all levels of cache up to the point of coherency, that is,to external memory.12.9.3 Cache usage profilingThere are two ways to obtain cache usage profiling information:• Statistic profiling using the Performance Monitoring Unit (PMU). The processorcan count cache accesses and misses over a period of time.• CP15 operations for accessing L1 and L2 cache tag and data arrays. Theseinstructions provide greater visibility into the cache state at the cost ofinterrupting the program flow to execute them.12-88 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E