Cortex-A8 R2P2.pdf - ARM Information Center

Cross Trigger Interface15.6 CTI register descriptionsThis section describes the CTI registers.15.6.1 CTI Control Register, CTICONTROLCTICONTROL is a read/write register that enables the CTI. Figure 15-4 shows the bitarrangement of the CTICONTROL Register.31 1 0ReservedGLBENBits Field FunctionFigure 15-4 CTI Control Register formatTable 15-4 shows how the bit values correspond with the CTICONTROL Registerfunctions.[31:1] - Reserved. RAZ, SBZ.Table 15-4 CTI Control Register bit functions[0] GLBEN Enables or disables the CTI:0 = disable CTI (reset)1 = enable CTI.When disabled, all cross triggering mapping logic functionality is disabled for this processor.15.6.2 CTI Interrupt Acknowledge Register, CTIINTACKCTIINTACK is a write-only register used to acknowledge the nCTIIRQ trigger output.When the nCTIIRQ trigger output is asserted, it continues to be asserted until you writeto bit [8] of this register.Figure 15-5 shows the bit arrangement of the CTIINTACK Register.31 9 8 70ReservedReservednCTIIRQ acknowledgeFigure 15-5 CTI Interrupt Acknowledge Register formatARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 15-13