Cortex-A8 R2P2.pdf - ARM Information Center

Instruction Cycle TimingExample 16-4 Advanced SIMD integer ALU instructionVADD.I32.S16 Q2, D1, D2This is an integer Advanced SIMD vector and long instruction. Source1, in this case D1,and Source2, in this case D2, are both required in N1. The result, stored in Q2 for thiscase, is available in N3 for the next subsequent instruction that requires this register asa source operand. Assuming no data hazards, the instruction takes a minimum of onecycle to execute as indicated by the value in the Cycles column.Example 16-5 shows how to read an Advanced SIMD floating-point multiplyinstruction from Table 16-18 on page 16-29.Example 16-5 Advanced SIMD floating-point multiply instructionVMUL.F32 Q0, Q1, D4[0]This is a floating-point Advanced SIMD vector multiply by scalar instruction. It is amulti-cycle instruction that has source operand requirements in both the first and secondcycles. In the first cycle, Source1, in this case Q1Lo or D2, is required in N2. Source2,in this case D4, is required in N1. In the second cycle, Source1, in this case Q1Hi or D3,is required in N2. The result of the multiply, stored in Q0 for this case, is available inN5 for the next subsequent instruction that requires this register as a source operand.The low half of the result, Q0Lo or D0, is calculated in the first cycle. The high half ofthe result, Q0Hi or D1, is calculated in the second cycle. Assuming no data hazards, theinstruction takes a minimum of two cycles to execute as indicated by the value in theCycles column.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 16-21