Cortex-A8 R2P2.pdf - ARM Information Center

DebugTable 12-4 shows the processor reset effect on debug and ETM logic.Table 12-4 Processor reset effect on debug and ETM logicSignal Debug power domain Core power domainDebug and ETM logic Debug and ETM logic Non-debug and non-ETM logicnPORESET Not reset Reset ResetARESETn Not reset Not reset ResetPRESETn Reset Reset Not reset12.3.8 APB interface access permissionsThe restrictions on accesses to the APB interface are described as follows:Privilege of memory accessThe system disables accesses to the memory-mapped registers based onthe privilege of the memory access.LocksThe debugger or software running on the system might lock out differentparts of the register map so they cannot be accessed while the debugsession is in certain states.Power downThe APB interface does not permit accesses to registers inside the corepower domain when the core powers down.Privilege of memory access permissionWhen nonprivileged software tries to access the APB interface, the system ignores orgenerates an abort response on the access. You must implement this restriction at thesystem level because the APB protocol does not have a control signal for privileged oruser access. You can choose to have the system either ignore or abort the access.Although you can place additional restrictions on the memory transactions that arepermitted to access the APB interface, ARM does not recommend this.12-12 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E