Cortex-A8 R2P2.pdf - ARM Information Center

Debug31 1 0ReservedOS unlock catchBits Field FunctionFigure 12-8 Event Catch Register formatTable 12-18 shows how the bit values correspond with the Event Catch Registerfunctions.[31:1] - Reserved. RAZ, SBZP.Table 12-18 Event Catch Register bit functions[0] OS unlock catch OS unlock catch:0 = catch disabled, reset value1 = catch enabled.When this bit is set to 1, the debug logic generates a debug event when the OS lock statetransitions from 1 to 0. This debug event might trigger a debug state entry, or might beignored, depending on the invasive debug security configuration. The OS unlock catchdebug event is a halting debug event and, therefore it cannot cause a debug exception.NoteIf you are debugging an application running on top of an OS that preserves the state of thedebug unit when powering down the core, this event indicates when the debug session cancontinue.12.4.10 Debug State Cache Control RegisterThe DSCCR controls both L1 and L2 cache behavior while the processor is in debugstate.Figure 12-9 on page 12-35 shows the bit arrangement of the DSCCR.See Cache debug on page 12-87 for information on the usage model of the DSCCRregister.12-34 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E