Cortex-A8 R2P2.pdf - ARM Information Center

Level 1 Memory System7.3 Memory attributesARMv7-A defines three memory regions using the TEX, C and B bits. They are:• Strongly ordered• Device• Normal.An access can be marked as shared. If it is marked as shared, the access is treated asnoncacheable.7.3.1 Strongly orderedStrongly ordered memory type is noncacheable, nonbufferable, and serialized. Thistype of memory flushes all buffers and waits for acknowledge from the bus beforeexecuting the next instruction. You must execute strongly ordered memorynonspeculatively. Unaligned accesses to strongly ordered memory result in analignment fault.7.3.2 DeviceDevice memory type is noncacheable and must be executed nonspeculatively. Orderingrequirement for device accesses are as follows:• device loads cannot bypass device stores• device stores can be buffered, but must be executed with respect to other devicestores• unaligned accesses to strongly ordered memory result in an alignment fault.7.3.3 NormalNormal memory type can have the following attributes:• noncacheable, bufferable• write-back cached, write-allocate• write-through cached, no allocate on write, buffered• write-back cached, no allocate on write, buffered.Table 7-1 on page 7-6 shows how L1 and L2 memory systems handle these memorytypes.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 7-5