Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorTable 3-23 shows how the bit values correspond with the Memory Model FeatureRegister 2 functions.Table 3-23 Memory Model Feature Register 2 bit functionsBits Field Function[31:28] Hardware accessflagIndicates support for hardware access flag:0x0 = Processor does not support hardware access flag.[27:24] WFI Indicates support for wait-for-interrupt stalling:0x1 = Processor supports wait-for-interrupt.[23:20] Memory barrierfeatures[19:16] Unified TLBmaintenanceoperations[15:12] Harvard TLBmaintenanceoperationsIndicates support for memory barrier operations.0x2 = Processor supports:• data synchronization barrier• instruction synchronization barrier• data memory barrier.Indicates support for TLB maintenance operations, unified architecture.0x0 = Processor does not support:• invalidate all entries• invalidate TLB entry by MVA• invalidate TLB entries by ASID match.Indicates support for TLB maintenance operations, Harvard architecture.0x2 = Processor supports:• invalidate instruction and data TLB, all entries• invalidate instruction TLB, all entries• invalidate data TLB, all entries• invalidate instruction TLB by MVA• invalidate data TLB by MVA• invalidate instruction and data TLB entries by ASID match• invalidate instruction TLB entries by ASID match• invalidate data TLB entries by ASID match.3-40 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E