Cortex-A8 R2P2.pdf - ARM Information Center

DebugTable 12-23 Breakpoint Control Registers bit functions (continued)Bits Field Function[4:3] - Reserved. RAZ, SBZP.[2:1] S Supervisor access control. The breakpoint can be conditioned on the mode of the processor:b00 = User, System, or Supervisorb01 = privilegedb10 = Userb11 = any.[0] B Breakpoint enable:0 = breakpoint disabled, reset value1 = breakpoint enabled.a. If BCR[28:24] is not set to b00000, then BCR[8:5] must be set to b1111. Otherwise, the behavior is Unpredictable. In addition,if BCR[28:24] is not set to b00000, then the corresponding BVR bits that are not being included in the comparisonShould-Be-Zero. Otherwise, the behavior is Unpredictable. If you program this BRP for context ID comparison, you must setthis field to b00000. Otherwise, the behavior is Unpredictable. There is no encoding for a full 32-bit mask but you can achievethe same effect of a break anywhere breakpoint by setting BCR[22] to 1 and BCR[8:5] to b0000.Table 12-24 Meaning of BVR bits [22:20]BVR[22:20]b000b001b010b011MeaningThe corresponding BVR[31:2] is compared against the IVA bus and the state of the processor against thisBCR. It generates a breakpoint debug event on a joint IVA and state match.The corresponding BVR[31:2] is compared against the IVA bus and the state of the processor against thisBCR. This BRP is linked with the one indicated by BCR[19:16] linked BRP field. They generate abreakpoint debug event on a joint IVA, context ID, and state match.The corresponding BVR[31:0] is compared against CP15 Context ID Register, c13 and the state of theprocessor against this BCR. This BRP is not linked with any other one. It generates a breakpoint debugevent on a joint context ID and state match. For this BRP, BCR[8:5] must be set to b1111. Otherwise, itis Unpredictable whether a breakpoint debug event is generated.The corresponding BVR[31:0] is compared against CP15 Context ID Register, c13. This BRP linksanother BRP (of the BCR[21:20]=b01 type), or WRP (with WCR[20]=b1). They generate a breakpointor watchpoint debug event on a joint IVA or DVA and context ID match. For this BRP, BCR[8:5] mustbe set to b1111, BCR[15:14] must be set to b00, and BCR[2:1] must be set to b11. Otherwise, it isUnpredictable whether a breakpoint debug event is generated.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 12-41