Cortex-A8 R2P2.pdf - ARM Information Center

Embedded Trace MacrocellTable 14-3 shows how the bit values correspond with the ID Register functions.Table 14-3 ID Register bit functionsBits Field Function[31:24] Implementor Indicates implementor, ARM:0x41.[23:20] - Reserved, RAZ.[19] Security ExtensionssupportIndicates Security Extensions support. The processor supports Security Extensionsarchitecture. If this bit is not set to 1, then the ETM behaves as if the processor is insecure state at all times.[18] Thumb-2 support All 32-bit Thumb instructions are traced as a single instruction, including BL and BLXimmediate.[17] - Reserved, RAZ.[16] Load pc first All data transfers are traced in the same order that they appear in the ARM ArchitectureReference Manual.[15:12] ARM core family Indicates the Cortex-A8 processor.[11:8] Major ETMarchitecture version[7:4] Minor ETMarchitecture versionIndicates the major ETM architecture version number, ETMv3.Indicates the minor ETM architecture version number, ETMv3.3.[3:0] Revision Indicates the implementation revision.14.4.2 Configuration Code RegisterThe Configuration Code Register, at offset 0x004, is a 32-bit read-only register thatprovides information about the configuration of the ETM. Figure 14-3 on page 14-12shows the bit arrangement for the Configuration Code Register.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 14-11