Cortex-A8 R2P2.pdf - ARM Information Center

DebugThe DTR access mode can be one of the following:• Nonblocking, this is the default mode• Stall• Fast.In Nonblocking mode, the APB reads from the DTRTX and writes to the DTRRX andITR are ignored if the appropriate READY flag is not set. In particular:• writes to DTRRX are ignored if DTRRXfull_l is set to 1• writes to ITR are ignored if InstrCompl_l is not set to 1• reads from DTRTX are ignored and return an Unpredictable value ifDTRTXfull_l is not set to 1.The debugger accessing these registers must first read the DSCR, and perform any ofthe following:• write to the DTRRX if the DTRRXfull_l flag was cleared to 0• write to the ITR if the InstrCompl_l flag was set to 1• read from the DTRTX if the DTRTXfull_l flag was set to 1.Failure to read the DSCR before one of these operations leads to Unpredictablebehavior.In Stall mode, the APB accesses to DTRRX, DTRTX, and ITR stall under the followingconditions:• writes to DTRRX are stalled until DTRRXfull is cleared to 0• writes to ITR are stalled until InstrCompl is set to 1• reads from DTRTX are stalled until DTRTXfull is set to 1.Fast mode is similar to Stall mode except that in Fast mode, the processor fetches aninstruction from the ITR when a DTRRX write or DTRTX read succeeds. In Stall modeand Nonblocking mode, the processor fetches an instruction from the ITR when an ITRwrite succeeds.12.4.6 Data Transfer RegisterThe DTR consists of two separate physical registers:• the DTRRX (Data Transfer Register - Receive)• the DTRTX (Data Transfer Register - Transmit).The register accessed is dependent on the instruction used:• writes, MCR and LDC instructions, access the DTRTX• reads, MRC and STC instructions, access the DTRRX.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 12-29