Cortex-A8 R2P2.pdf - ARM Information Center

Instruction Cycle TimingTable 16-19 Advanced SIMD byte permute instructions (continued)Instruction Register format Cycles Source Result1 2 3 4 1 2VTBX Dd,{Dn},Dm 12Dd:N1Dn:N1Dm:N1------Dd:N2--Dd,{Dn,Dn1},Dm 12Dd:N1Dn:N1Dm:N1Dn1:N1-----Dd:N2--Dd,{Dn,Dn1,Dn2},Dm 123Dd:N1Dn:N1Dn2:N1Dm:N1Dn1:N1---------Dd:N2---Dd,{Dn,Dn1,Dn2,Dn3},Dm 123Dd:N1Dn:N1Dn2:N1Dm:N1Dn1:N1Dn3:N1--------Dd:N2---16.6.7 Advanced SIMD load/store instructionsAdvanced SIMD load/store instructions can be divided into the followingsubcategories:• VLDR and VSTR register load/store single• VLDM and VSTM register load/store multiple• VLD and VST multiple 1-element or 2, 3, 4-element structure• VLD and VST single 1-element or 2, 3, 4-element structure to one lane• VLD single 1-element or 2, 3, 4-element structure to all lanes.VLDR and VSTR instructions transfer a single 64-bit register and require two issue cycles.Processor scheduling is static, and it is not possible to know the address alignment atschedule time. Therefore, scheduling of the VLDR and VSTR instructions must be doneassuming the load/store address is not 128-bit aligned.VLDM and VSTM instructions transfer multiple 64-bit registers. The number of registers inthe register list determines the number of cycles required to execute a load or storemultiple. The NEON unit can load or store two 64-bit registers in each cycle. Thenumber of cycles required to execute a VLDM or VSTM instruction is given by the followingformula:(number of registers/2) + mod (number of registers,2) + 116-32 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E