Cortex-A8 R2P2.pdf - ARM Information Center

Level 2 Memory System8.2 Cache organizationThe L2 cache is 8-way set associative of configurable size. The cache is physicallyaddressed. The cache sizes are configurable with sizes in the range of 0KB, 128KB,256KB, 512KB, and 1MB.You can reduce the effective cache size using lockdown format C. This feature enablesyou to lock cache ways to prevent allocation to locked entries.You can configure the L2 memory pipeline to insert wait states to take into account thelatencies of the compiled memories for the implemented RAMs.To enable streaming of NEON read accesses from the L1 data cache, the L2 memorysystem supports up to twelve NEON read accesses. The write buffer handles integerwrites, NEON writes, and eviction accesses from the L1 data cache. This enablesstreaming of write requests from the L1 data cache.The L2 cache incorporates a dirty bit per quadword to reduce AXI traffic. Thiseliminates unnecessary transfer of clean data on the AXI interface.8.2.1 L2 cache bank structureThe L2 cache is partitioned into multiple banks to enable parallel operations. There aretwo levels of banking:• the tag array is partitioned into multiple banks to enable up to two requests toaccess different tag banks of the L2 cache simultaneously• each tag bank is partitioned into multiple data banks to enable streaming accessesto the data banks.Figure 8-1 on page 8-4 shows the logical representation of the L2 cache bank structure.The diagram shows a configuration with all possible tag and data bank combinations.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 8-3