Cortex-A8 R2P2.pdf - ARM Information Center

System Control Coprocessor31 8 7 6 5 4 3 2 1 0ReservedLOCK way-7LOCK way-6LOCK way-5LOCK way-4LOCK way-3LOCK way-2LOCK way-1LOCK way-0Figure 3-48 L2 Cache Lockdown Register formatTable 3-106 shows how the bit values correspond with the L2 Cache LockdownRegister functions.Bits Field Function[31:8] - Reserved. UNP, SBZP.Table 3-106 L2 Cache Lockdown Register bit functions[7] LOCKway-7[6] LOCKway-6[5] LOCKway-5[4] LOCKway-4[3] LOCKway-3Lockdown bit for way 7 of the L2 cache:0 = way 7 is not locked and allocation is determined by standard replacement algorithm1 = way 7 is locked and no allocation is performed to this cache way.Lockdown bit for way 6 of the L2 cache:0 = way 6 is not locked and allocation is determined by standard replacement algorithm1 = way 6 is locked and no allocation is performed to this cache way.Lockdown bit for way 5 of the L2 cache:0 = way 5 is not locked and allocation is determined by standard replacement algorithm1 = way 5 is locked and no allocation is performed to this cache way.Lockdown bit for way 4 of the L2 cache:0 = way 4 is not locked and allocation is determined by standard replacement algorithm1 = way 4 is locked and no allocation is performed to this cache way.Lockdown bit for way 3 of the L2 cache:0 = way 3 is not locked and allocation is determined by standard replacement algorithm1 = way 3 is locked and no allocation is performed to this cache way.3-122 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E