Cortex-A8 R2P2.pdf - ARM Information Center

System Control Coprocessor31 28 27 12 8 7 3 0ReservedBranch predictor maintenanceHierarchical cache maintenance operations by set and wayHierarchical cache maintenance operations by MVASupersectionFigure 3-10 Memory Model Feature Register 3 formatTable 3-25 shows how the bit values correspond with the Memory Model FeatureRegister 3 functions.Table 3-25 Memory Model Feature Register 3 bit functionsBits Field Function[31:28] Supersection Indicates support for supersections:0x0 = Processor supports supersections.[27:12] - Reserved, RAZ.[11:8] Branch predictormaintenance[7:4] Hierarchical cachemaintenance operationsby set and way[3:0] Hierarchical cachemaintenance operationsby MVAIndicates support for branch predictor maintenance operations:0x2 = Processor supports invalidate entire branch predictor array and invalidatebranch predictor by MVA.Indicates support for invalidate cache by set and way, clean by set and way, andinvalidate and clean by set and way:0x1 = Processor supports invalidate cache by set and way, clean by set and way, andinvalidate and clean by set and way.Indicates support for invalidate cache by MVA, clean by MVA, invalidate andclean by MVA, and invalidate all:0x1 = Processor supports invalidate cache by MVA, clean by MVA, invalidate andclean by MVA, and invalidate all.Table 3-26 shows the results of attempted access for each mode.Table 3-26 Results of access to Memory Model Feature Register 3 aSecure privileged Nonsecure privileged Secure User Nonsecure UserRead Write Read Write Read Write Read WriteData Undefined Data Undefined Undefined Undefined Undefined Undefined3-42 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E