Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorTable 3-11 shows the results of attempted access for each mode.Table 3-11 Results of access to the Multiprocessor ID Register aSecure privileged Nonsecure privileged Secure User Nonsecure UserRead Write Read Write Read Write Read WriteData Undefined Data Undefined Undefined Undefined Undefined Undefineda. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessorinstruction is executed.To access the Multiprocessor ID Register, read CP15 with:MRC p15, 0, , c0, c0, 5; Read Multiprocessor ID Register3.2.7 c0, Processor Feature Register 0The purpose of Processor Feature Register 0 is to provide information about theexecution state support and programmer’s model for the processor.The Processor Feature Register 0 is:• a read-only register common to the Secure and Nonsecure states• accessible in privileged modes only.Figure 3-4 shows the bit arrangement of the Processor Feature Register 0.31 16 15 12 11 8 7 4 3 0ReservedState3State2 State1 State0Figure 3-4 Processor Feature Register 0 format3-30 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E