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Design for Test4. rscan array, data_seed = invert.Figure 11-14 shows the physical array after the first COLBAR pass.Rowmaxmax - 1Addressingdirection0 1 0 10 1 0 10 10 132100 1 0 10 1 0 10 1 0 10 1 0 10 10 10 10 1Col 0 1 2 3maxmax - 1Figure 11-14 Physical array after pass 1 of COLBARROWBARROWBAR is a row-fast bar-stripe scan pattern in which the following conditiondetermines data seed inversion:invert = row_index[0]ROWBAR performs the following sequence:1. wscan array, data_seed = true.2. rscan array, data_seed = true.3. wscan array, data_seed = invert.4. rscan array, data_seed = invert.Figure 11-15 on page 11-29 shows the physical array after the first ROWBAR pass.11-28 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E
Design for TestRowmaxmax - 11 1 1 10 0 0 01 10 0Addressingdirection32101 1 1 10 0 0 01 1 1 10 0 0 0Col 0 1 2 31 10 01 10 0maxmax - 1Figure 11-15 Physical array after pass 1 of ROWBARSOLIDSSOLIDS is a row-fast scan pattern in which data seed inversion is not a function ofaddress.SOLIDS performs the following sequence:1. wscan array, data_seed = true.2. rscan array, data_seed = true.3. wscan array, data_seed = invert.4. rscan array, data_seed = invert.RWXMARCHRWXMARCH is a row-fast RW increment/decrement march. It performs the followingsequence:1. wscan data to entire array.2. R, W_, incr.3. R_, W, decr.4. rscan data from entire array.Figure 11-16 on page 11-30 shows the state of row 1, column 2 in a 4 4 array duringpass 2.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 11-29
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Cortex -A8Revision: r2p2Technical R
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Product StatusThe information in th
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ContentsCortex-A8 Technical Referen
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Contents7.8 Parity detection ......
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ContentsA.2 ATB interface .........
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List of TablesCortex-A8 Technical R
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List of TablesTable 3-103 Results o
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List of TablesTable 12-1 Access to
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List of TablesTable 15-3 CTI regist
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List of Tablesxx Copyright © 2006-
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List of FiguresFigure 3-10 Memory M
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List of FiguresFigure 10-13 Retenti
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List of FiguresFigure 15-16 CTI Cha
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PrefaceAbout this manualThis is the
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PrefaceChapter 16 Instruction Cycle
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PrefacePrefix CPrefix HPrefix nPref
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PrefaceFeedbackARM welcomes feedbac
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Introduction1.1 About the processor
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Introduction1.3 Components of the p
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Introduction1.3.4 Load/storeThe loa
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Introduction1.4 External interfaces
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Introduction1.6 Power managementThe
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Introduction1.8 Product revisionsTh
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Introduction1-14 Copyright © 2006-
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Programmer’s Model• Hardware co
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Programmer’s Model2.2 Thumb-2 ins
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Programmer’s Model2.3 ThumbEE ins
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Programmer’s ModelThumbEE Handler
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Programmer’s Model2.4 Jazelle Ext
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Programmer’s Model— the registe
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Programmer’s ModelNonsecureSecure
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Programmer’s Model2.7 VFPv3 archi
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Programmer’s Model2.9 Data typesT
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Programmer’s ModelBitHigher addre
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Programmer’s Model2.12 Operating
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Programmer’s ModelIn privileged m
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Programmer’s Model16 generalpurpo
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Programmer’s ModelIn ARM state, y
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Programmer’s Model2.14.5 The GE[3
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Programmer’s ModelT bitThe T bit
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Programmer’s ModelOnly secure pri
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Programmer’s Model2.15.2 Leaving
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Programmer’s ModelAn internal or
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Programmer’s ModelImprecise data
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Programmer’s ModelNoteIf the Embe
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Programmer’s Model2.16 Software c
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Programmer’s Model2.17.2 Security
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Programmer’s Model2.18 Control co
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System Control Coprocessor3.1 About
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System Control CoprocessorTable 3-1
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System Control CoprocessorSecurity
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System Control Coprocessor3.1.6 Sys
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System Control Coprocessor3.2.20 c0
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System Control CoprocessorThe Auxil
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System Control Coprocessorb. The EN
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System Control Coprocessor• acces
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System Control CoprocessorYou can c
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System Control CoprocessorTo access
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System Control CoprocessorTo access
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System Control CoprocessorThe PLE I
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System Control CoprocessorLDR R1, =
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System Control CoprocessorLDR R1, =
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System Control CoprocessorL1 Data 0
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System Control CoprocessorInstructi
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System Control CoprocessorParity/EC
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System Control CoprocessorL2 parity
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System Control CoprocessorThe L2 da
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Chapter 4Unaligned Data and Mixed-e
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Unaligned Data and Mixed-endian Dat
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Unaligned Data and Mixed-endian Dat
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Chapter 5Program Flow PredictionThi
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Program Flow Prediction5.2 Predicte
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Program Flow Prediction5.2.1 Return
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Program Flow Prediction5.4 Guidelin
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Program Flow Prediction5.6 Operatin
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Chapter 6Memory Management UnitThis
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Memory Management Unit6.2 Memory ac
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Memory Management Unit6.4 MMU inter
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Memory Management Unit6.6 TLB lockd
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Chapter 7Level 1 Memory SystemThis
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Level 1 Memory System7.2 Cache orga
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Level 1 Memory System7.3 Memory att
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Level 1 Memory SystemTable 7-1 Memo
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Level 1 Memory System7.5 Data cache
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Level 1 Memory SystemAn exception t
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Level 1 Memory System7.8 Parity det
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Chapter 8Level 2 Memory SystemThis
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Level 2 Memory System8.2 Cache orga
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Level 2 Memory System8.3 Enabling a
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Level 2 Memory SystemControl Regist
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Level 2 Memory System8.4.4 Memory r
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Level 2 Memory System8.5 Synchroniz
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Chapter 9External Memory InterfaceT
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External Memory Interfaceto the wri
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External Memory InterfaceTable 9-2
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External Memory Interface9.3 AXI in
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External Memory InterfaceBWBCNoTTSS
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Chapter 10Clock, Reset, and Power C
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Clock, Reset, and Power Controlfami
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Clock, Reset, and Power Control10.2
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Debug12.4.16 Watchpoint Control Reg
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DebugNoteOn system reset, PRSR[1] r
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DebugTable 12-32 Management registe
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Debug12.5.5 Integration Mode Contro
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Debug31 8 7 6 5 4 3 2 1 0ReservedSe
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DebugTable 12-44 Peripheral Identif
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Debug12.6.5 Watchpoint debug events
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DebugNoteThe Data Abort handler che
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DebugTable 12-54 shows the read PC
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Debug12.8.4 Writing to the CPSR in
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DebugCoprocessor instructionsThe ru
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Debug12.9 Cache debugThere are seve
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DebugDBGROMADDRThe DBGROMADDR signa
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Debug4. Issue an Instruction Synchr
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Debug12.11.1 Debug communications c
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DebugDebugger access to the DCCA de
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DebugNoteIn Example 12-10 on page 1
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Chapter 13NEON and VFP Programmer
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NEON and VFP Programmer’s Modelre
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Chapter 16Instruction Cycle TimingT
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AC Characteristics17.5 L1 and L2 MB
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AC Characteristics17.7 DFT interfac
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AC Characteristicsb. Figure 10-6 on
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Appendix ASignal DescriptionsThis a
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Signal DescriptionsA.2 ATB interfac
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Signal DescriptionsTable A-3 MBIST
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Signal DescriptionsA.4 Preload engi
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Signal DescriptionsA.8 Miscellaneou
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Appendix BInstruction MnemonicsThis
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Instruction MnemonicsB.2 VFP data-p
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GlossaryThis glossary describes som
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GlossaryApplication Specific Integr
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GlossaryRead ID capabilityThe maxim
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GlossaryCAM includes comparison log
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GlossaryDouble-precision valueConsi
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Glossary• arithmetic operation re
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GlossaryInvalidateJazelle architect
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GlossaryPAPenaltyPower-on resetPref
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GlossarySetSet-associative cacheSee
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GlossaryTrapTrigger instructionAn e
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GlossaryWrite-back (WB)Write buffer
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