Cortex-A8 R2P2.pdf - ARM Information Center

Clock, Reset, and Power ControlPowering up the integer core power domain while keeping NEON powereddownApply the following sequence to power up the integer core while keeping NEONpowered down:1. Apply power to the integer core power domain while keeping ARESETn,ARESETNEONn and nPORESET asserted. Be sure to keep the NEON powerdomain off.2. Release the clamps to the debug PCLK, ETM CLK, and ETM ATCLK powerdomains from the core by deasserting CLAMPCOREOUT and keepingCLAMPNEONOUT asserted.3. Deassert DBGPWRDWNREQ to indicate that processor debug and ETMresources are available. There is no requirement for hardware to wait forDBGPWRDWNACK to be deasserted.NoteThe ETMPWRDWNREQ and ETMPWRDWNACK signals are not requiredbecause debug and the ETM use the same power domain. ETMPWRDWNREQmust be tied to 0.4. Continue a normal power-on reset sequence while ARESETNEONn andCLAMPNEONOUT remain asserted. To power up the NEON power domain,see Powering up the NEON power domain while the processor is not in reset onpage 10-22.10.3.4 L1 data and L2 cache power domainsDuring periods when the entire core is not required, you can stop the processor clocksby executing a Wait For Interrupt instruction. However, leakage continues to occur. Toremove the leakage component, you must remove the power supplied to the powerdomains within the processor. However, the time required to remove and restore thepower limits the advantage of a full power-down of the processor. A full power-downsequence for the processor might include:1. Clean and invalidate the caches, L1 data and L2 caches, to the point of coherency.2. Disable the L1 data and L2 cache.3. Save off any TLB state such as locked entries, if required.4. Save off architectural state.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 10-25