Cortex-A8 R2P2.pdf - ARM Information Center

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NEON and VFP Programmer’s ModelAny SNaN passed as input to an operation causes an Invalid Operation exception andsets the IOC flag, FPSCR[0], to 1. A default QNaN is written to the destination register.The rules for cases involving multiple NaN operands are in the ARM ArchitectureReference Manual.Processing of input NaNs for ARM floating-point coprocessors and libraries is definedas follows:• In full-compliance mode, NaNs are handled according to the ARM ArchitectureReference Manual. The hardware processes the NaNs directly for arithmetic CDPinstructions. For data transfer operations, NaNs are transferred without raising theInvalid Operation exception. For the non-arithmetic CDP instructions, FABS, FNEG,and FCPY, NaNs are copied, with a change of sign if specified in the instructions,without causing the Invalid Operation exception.• In default NaN mode, NaNs are handled completely within the hardware. SNaNsin an arithmetic CDP operation set the IOC flag, FPSCR[0], to 1. NaN handlingby data transfer and non-arithmetic CDP instructions is the same as infull-compliance mode. Arithmetic CDP instructions involving NaN operandsreturn the default NaN regardless of the fractions of any NaN operands.Table 13-14 summarizes the effects of NaN operands on instruction execution.Table 13-14 QNaN and SNaN handlingInstructiontypeDefaultNaNmode With QNaN operand With SNaN operandArithmetic CDPOffThe QNaN or one of the QNaN operands, ifthere is more than one, is returnedaccording to the rules given in the ARMArchitecture Reference Manual.IOC a set to 1. The SNaN is quieted and theresult NaN is determined by the rules givenin the ARM Architecture ReferenceManual.On Default NaN returns. IOC b set to 1. Default NaN returns.Non-arithmeticCDPOffOnNaN passes to destination with sign changed as appropriate.FCMP(Z) - Unordered compare. IOC set to 1. Unordered compare.FCMPE(Z) - IOC set to 1. Unordered compare. IOC set to 1. Unordered compare.Load/storeOffOnAll NaNs transferred.a. IOC is the Invalid Operation exception flag, FPSCR[0].13-24 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E
NEON and VFP Programmer’s ModelComparisonsComparison results modify condition code flags in the FPSCR Register. The FMSTATinstruction transfers the current condition code flags in the FPSCR Register to the CPSRRegister. See the ARM Architecture Reference Manual for more information. Thecondition code flags used are chosen so that subsequent conditional execution of ARMinstructions can test the predicates defined in the IEEE 754 standard.The VFP coprocessor handles all comparisons of numeric and reserved values inhardware, generating the appropriate condition code depending on whether the result isless than, equal to, or greater than.The VFP coprocessor supports:Compare operationsThe compare operations are FCMPS, FCMPZS, FCMPD, and FCMPZD.A compare instruction involving a QNaN produces an unordered result.An SNaN produces an unordered result and generates an InvalidOperation exception.Compare with exception operationsThe compare with exception operations are FCMPES, FCMPEZS, FCMPED, andFCMPEZD.A compare with exception operation involving either an SNaN or aQNaN produces an unordered result and generates an Invalid Operationexception.UnderflowIn the generation of Underflow exceptions, the before rounding form of tininess and theinexact result form of loss of accuracy as described in the IEEE 754 standard, are used.In flush-to-zero mode, results that are tiny before rounding, as described in the IEEE754 standard, are flushed to a zero, and the UFC flag, FPSCR[3], is set to 1. See theARM Architecture Reference Manual for information on flush-to-zero mode.When the VFP coprocessor is not in flush-to-zero mode, operations are performed onsubnormal operands. If the operation does not produce a tiny result, it returns thecomputed result, and the UFC flag, FPSCR[3], is not set to 1. The IXC flag, FPSCR[4],is set to 1 if the operation is inexact. If the operation produces a tiny result, the result isa subnormal or zero value, and the UFC flag, FPSCR[3], is set to 1.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 13-25
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Cortex -A8Revision: r2p2Technical R
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Product StatusThe information in th
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ContentsCortex-A8 Technical Referen
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Contents7.8 Parity detection ......
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ContentsA.2 ATB interface .........
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List of TablesCortex-A8 Technical R
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List of TablesTable 3-103 Results o
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List of TablesTable 12-1 Access to
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List of TablesTable 15-3 CTI regist
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List of Tablesxx Copyright © 2006-
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List of FiguresFigure 3-10 Memory M
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List of FiguresFigure 10-13 Retenti
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List of FiguresFigure 15-16 CTI Cha
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PrefaceAbout this manualThis is the
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PrefaceChapter 16 Instruction Cycle
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PrefacePrefix CPrefix HPrefix nPref
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PrefaceFeedbackARM welcomes feedbac
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Introduction1.1 About the processor
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Introduction1.3 Components of the p
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Introduction1.3.4 Load/storeThe loa
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Introduction1.4 External interfaces
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Introduction1.6 Power managementThe
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Introduction1.8 Product revisionsTh
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Introduction1-14 Copyright © 2006-
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Programmer’s Model• Hardware co
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Programmer’s Model2.2 Thumb-2 ins
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Programmer’s Model2.3 ThumbEE ins
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Programmer’s ModelThumbEE Handler
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Programmer’s Model2.4 Jazelle Ext
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Programmer’s Model— the registe
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Programmer’s ModelNonsecureSecure
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Programmer’s Model2.7 VFPv3 archi
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Programmer’s Model2.9 Data typesT
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Programmer’s ModelBitHigher addre
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Programmer’s Model2.12 Operating
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Programmer’s ModelIn privileged m
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Programmer’s Model16 generalpurpo
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Programmer’s ModelIn ARM state, y
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Programmer’s Model2.14.5 The GE[3
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Programmer’s ModelT bitThe T bit
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Programmer’s ModelOnly secure pri
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Programmer’s Model2.15.2 Leaving
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Programmer’s ModelAn internal or
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Programmer’s ModelImprecise data
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Programmer’s ModelNoteIf the Embe
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Programmer’s Model2.16 Software c
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Programmer’s Model2.17.2 Security
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Programmer’s Model2.18 Control co
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System Control Coprocessor3.1 About
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System Control CoprocessorTable 3-1
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System Control CoprocessorSecurity
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System Control Coprocessor3.1.6 Sys
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System Control Coprocessor3.2.20 c0
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System Control Coprocessora. An ent
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System Control CoprocessorThe Auxil
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System Control CoprocessorBits Fiel
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System Control Coprocessora. n is t
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System Control CoprocessorVA to PA
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System Control CoprocessorInvalidat
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System Control CoprocessorThe PMNC
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System Control CoprocessorCWhen wri
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System Control Coprocessorb. The EN
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System Control Coprocessor• acces
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System Control CoprocessorYou can c
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System Control CoprocessorIf the op
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System Control CoprocessorTo access
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System Control Coprocessora. An ent
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System Control CoprocessorTo access
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System Control CoprocessorThe PLE I
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System Control CoprocessorLDR R1, =
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System Control CoprocessorLDR R1, =
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System Control CoprocessorL1 Data 0
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System Control CoprocessorInstructi
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System Control CoprocessorParity/EC
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System Control CoprocessorL2 parity
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System Control CoprocessorThe L2 da
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Chapter 4Unaligned Data and Mixed-e
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Unaligned Data and Mixed-endian Dat
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Unaligned Data and Mixed-endian Dat
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Chapter 5Program Flow PredictionThi
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Program Flow Prediction5.2 Predicte
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Program Flow Prediction5.2.1 Return
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Program Flow Prediction5.4 Guidelin
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Program Flow Prediction5.6 Operatin
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Chapter 6Memory Management UnitThis
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Memory Management Unit6.2 Memory ac
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Memory Management Unit6.4 MMU inter
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Memory Management Unit6.6 TLB lockd
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Chapter 7Level 1 Memory SystemThis
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Level 1 Memory System7.2 Cache orga
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Level 1 Memory System7.3 Memory att
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Level 1 Memory SystemTable 7-1 Memo
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Level 1 Memory System7.5 Data cache
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Level 1 Memory SystemAn exception t
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Level 1 Memory System7.8 Parity det
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Chapter 8Level 2 Memory SystemThis
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Level 2 Memory System8.2 Cache orga
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Level 2 Memory System8.3 Enabling a
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Level 2 Memory SystemControl Regist
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Level 2 Memory System8.4.4 Memory r
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Level 2 Memory System8.5 Synchroniz
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Level 2 Memory System8.6 Locked acc
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Chapter 9External Memory InterfaceT
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External Memory Interfaceto the wri
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External Memory InterfaceTable 9-2
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External Memory Interface9.3 AXI in
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External Memory InterfaceBWBCNoTTSS
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Chapter 10Clock, Reset, and Power C
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Clock, Reset, and Power Controlfami
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Clock, Reset, and Power Control10.2
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Clock, Reset, and Power Control•
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Clock, Reset, and Power Control2. F
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Clock, Reset, and Power ControlNote
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Clock, Reset, and Power ControlAfte
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Clock, Reset, and Power Control•
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Clock, Reset, and Power Control—
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Clock, Reset, and Power ControlThe
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Clock, Reset, and Power ControlPowe
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Clock, Reset, and Power ControlTo p
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Clock, Reset, and Power ControlATBI
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Clock, Reset, and Power Control7. P
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Chapter 11Design for TestThis chapt
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Design for Test11.1.2 MBIST registe
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Design for Testdseed[3:0]Write the
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Design for TestNoteOnly arrays with
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Design for Test• read and write l
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Design for TestTable 11-10 Selectin
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Design for TestTable 11-15 shows ho
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Design for TestArrayFail[22:0] fail
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Design for TestWhen testing the tag
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Design for Test• Bitmap test mode
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Design for TestCLKARESETnMBISTMODEM
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Design for TestCLKARESETnMBISTMODEM
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Design for TestTable 11-19 shows th
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Design for TestNoteNormal MBIST tes
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Design for Test2. R, W_, R_, incr.3
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Design for TestRow3210Addressingdir
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Design for Test11.2 ATPG test featu
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Design for TestWBR in place of the
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Design for TestOne methodology for
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Chapter 12DebugThis chapter describ
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Debug12.1.3 Debug targetThe debug t
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DebugWhen execution of a monitor ta
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Debug12.3 Debug register interfaceY
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DebugTable 12-3 Debug memory-mapped
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Debug12.3.6 Power domains and debug
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DebugLocks permissionYou can lock t
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DebugTable 12-6 shows the behavior
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Debug12.4 Debug register descriptio
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DebugTable 12-11 shows how the bit
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DebugThe Debug Self Address Offset
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DebugBits Field FunctionTable 12-14
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DebugBits Field Function[9] - Reser
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DebugThe DTR access mode can be one
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DebugBitsFieldFunctionTable 12-16 s
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DebugTable 12-17 Vector Catch Regis
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Debug31 3 2 1 0ReservedNot write-th
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Debug12.4.16 Watchpoint Control Reg
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DebugTable 12-26 Watchpoint Control
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DebugNoteOn system reset, PRSR[1] r
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DebugTable 12-32 Management registe
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Debug12.5.5 Integration Mode Contro
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Debug31 8 7 6 5 4 3 2 1 0ReservedSe
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DebugTable 12-44 Peripheral Identif
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DebugTable 12-50 shows how the bit
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Debug12.6.2 Halting debug event•
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Debug12.6.5 Watchpoint debug events
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DebugNoteThe Data Abort handler che
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DebugIf the debugged code is not ru
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DebugTable 12-54 shows the read PC
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Debug12.8.4 Writing to the CPSR in
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DebugCoprocessor instructionsThe ru
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DebugDBGROMADDRThe DBGROMADDR signa
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Cross Trigger Interface15.6 CTI reg
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Cross Trigger InterfaceNoteThe CTII
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Cross Trigger InterfaceActual Compo
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Chapter 16Instruction Cycle TimingT
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Instruction Cycle Timing16.2 Instru
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Instruction Cycle Timing16.2.7 Stat
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Instruction Cycle TimingThe number
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Instruction Cycle Timing16.3 Dual-i
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Instruction Cycle TimingReplayevent
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Instruction Cycle TimingPredicting
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Instruction Cycle TimingExample 16-
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Instruction Cycle Timing16.6.3 Adva
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Instruction Cycle Timing16.7 VFP in
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AC CharacteristicsTable 17-2 Timing
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AC Characteristics17.4 APB interfac
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AC Characteristics17.5 L1 and L2 MB
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AC Characteristics17.7 DFT interfac
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AC Characteristicsb. Figure 10-6 on
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Appendix ASignal DescriptionsThis a
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Signal DescriptionsA.2 ATB interfac
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Signal DescriptionsTable A-3 MBIST
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Signal DescriptionsA.4 Preload engi
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Signal DescriptionsTable A-7 Miscel
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Signal DescriptionsA.8 Miscellaneou
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Appendix BInstruction MnemonicsThis
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Instruction MnemonicsTable B-1 Adva
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Instruction MnemonicsB.2 VFP data-p
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GlossaryThis glossary describes som
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GlossaryApplication Specific Integr
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GlossaryRead ID capabilityThe maxim
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GlossaryByte-invariantIn a byte-inv
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GlossaryCAM includes comparison log
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GlossaryDouble-precision valueConsi
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Glossary• arithmetic operation re
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GlossaryInvalidateJazelle architect
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GlossaryPAPenaltyPower-on resetPref
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GlossarySetSet-associative cacheSee
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GlossaryTrapTrigger instructionAn e
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GlossaryWrite-back (WB)Write buffer
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