Cortex-A8 R2P2.pdf - ARM Information Center

DebugTable 12-33 Processor Identifier Registers (continued)OffsetRegisternumberMnemonicFunction0xD24 841 ID_PFR1 Processor Feature Register 1, see c0, Processor Feature Register 1 onpage 3-310xD28 842 ID_DFR0 Debug Feature Register 0, see c0, Debug Feature Register 0 on page 3-330xD2C 843 ID_AFR0 Auxiliary Feature Register 0, see c0, Auxiliary Feature Register 0 onpage 3-340xD30 844 ID_MMFR0 Memory Model Feature Register 0, see c0, Memory Model FeatureRegister 0 on page 3-350xD34 845 ID_MMFR1 Memory Model Feature Register 1, see c0, Memory Model FeatureRegister 1 on page 3-370xD38 846 ID_MMFR2 Memory Model Feature Register 2, see c0, Memory Model FeatureRegister 2 on page 3-390xD3C 847 ID_MMFR3 Memory Model Feature Register 3, see c0, Memory Model FeatureRegister 3 on page 3-410xD40 848 ID_ISAR0 Instruction Set Attributes Register 0, see c0, Instruction Set AttributesRegister 0 on page 3-430xD44 849 ID_ISAR1 Instruction Set Attributes Register 1, see c0, Instruction Set AttributesRegister 1 on page 3-440xD48 850 ID_ISAR2 Instruction Set Attributes Register 2, see c0, Instruction Set AttributesRegister 2 on page 3-460xD4C 851 ID_ISAR3 Instruction Set Attributes Register 3, see c0, Instruction Set AttributesRegister 3 on page 3-480xD50 852 ID_ISAR4 Instruction Set Attributes Register 4, see c0, Instruction Set AttributesRegister 4 on page 3-500xD54 853 ID_ISAR5 Instruction Set Attributes Register 5, see c0, Instruction Set AttributesRegisters 5-7 on page 3-5212.5.2 Integration Internal Output Control RegisterWhen the processor is in integration mode, you can use the read/write IntegrationInternal Output Control Register to drive certain debug unit outputs to determine howthey are connected to the Cross Triggered Interface (CTI).12-56 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E