Cortex-A8 R2P2.pdf - ARM Information Center

System Control Coprocessora. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when thecoprocessor instruction is executed.To access the PLE User Accessibility Register, read or write CP15 with:MRC p15, 0, , c11, c1, 0 ; Read PLE User Accessibility RegisterMCR p15, 0, , c11, c1, 0 ; Write PLE User Accessibility RegisterThe registers that you can access in User mode when the U1 or U0 bit = 1 for the currentchannel are:• c11, PLE enable commands on page 3-143• c11, PLE Control Register on page 3-143• c11, PLE Internal Start Address Register on page 3-147• c11, PLE Internal End Address Register on page 3-148• c11, PLE Channel Status Register on page 3-150.You can access the PLE Channel Number Register, see c11, PLE Channel NumberRegister, in User mode when the U1 or U0 bit for any channel is 1.The contents of these registers must be preserved on a task switch if the registers areuser accessible.If the U bit for the currently selected channel is set to 0, and a User mode processattempts to access any of these registers, the processor takes an Undefined instructiontrap.3.2.61 c11, PLE Channel Number RegisterThe purpose of the PLE Channel Number Register is to select a PLE channel.The PLE Channel Number Register is:• a read/write register common to Secure and Nonsecure states• accessible in User and privileged modes.Figure 3-55 shows the bit arrangement of the PLE Channel Number Register.31 1 0ReservedCNFigure 3-55 PLE Channel Number Register formatARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 3-141