Cortex-A8 R2P2.pdf - ARM Information Center

Clock, Reset, and Power ControlPowering down the NEON power domain while the processor is not in resetTo power down the NEON power domain while the processor is not in reset, the NEONpower domain must be placed into an idle state. Apply the following sequence to placethe NEON power domain into an idle state:1. Software must disable access to the NEON unit using the Coprocessor AccessControl Register, see c1, Coprocessor Access Control Register on page 3-67. Alloutstanding Advanced SIMD instructions retire and all subsequent AdvancedSIMD instruction cause an Undefined Instruction exception.MRC p15, 0, , c1, c0, 2; Read Coprocessor Access Control RegisterBIC , , #0xF00000; Disable access to CP10 and CP11MCR p15, 0, , c1, c0, 2; Write Coprocessor Access Control Register2. Software must signal to the external system that the NEON unit is disabled.3. Assert ARESETNEONn to place NEON in reset. You must assertARESETNEONn for at least eight CLK cycles before activating the NEONclamps.4. Activate the NEON output clamps by asserting the CLAMPNEONOUT inputHIGH.5. Remove power from the NEON power domain.NoteIf ARESETNEONn is deasserted or the NEON output clamps are released withoutfollowing one of the specified NEON power-up sequences, the results areUnpredictable and might cause the processor to deadlock.Powering up the NEON power domain while the processor is in resetTo apply power to the NEON power domain while the processor is in reset, use thefollowing sequence:1. Assert ARESETn and keep ARESETNEONn asserted.2. Apply power to the NEON power domain.3. Release the NEON output clamps by deasserting CLAMPNEONOUT.4. Deassert ARESETn and ARESETNEONn.After the completion of the reset sequence, you can enable the NEON unit using theCoprocessor Access Control Register. See c1, Coprocessor Access Control Register onpage 3-67.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 10-21