Cortex-A8 R2P2.pdf - ARM Information Center

Clock, Reset, and Power Control7. Perform a software read of a memory location to determine that the L1 data cacheand L2 cache have valid data and to skip the software initialization sequence.8. Before enabling the L1 data cache or L2 cache, or using any CP15 cache-relatedoperations, software must signal the system to release the L1 data cache and L2cache input clamps and receive confirmation that the clamps have been released.NoteThe details of how to clamp the inputs to various arrays are implementation-specific andare not described in this document. Care must be taken that nPORESET does not affectthe state in the RAM arrays.10.3.5 Special note on reset during power transitionDuring any transition of the power supply to a component of the processor, theasynchronous reset to that component must be asserted. This is a safety mechanism forimplementation to ensure that hardware can be protected against supply transition, DCpaths, such as precharge or discharge circuits, or bus contention. The primary inputs tothe processor that act as asynchronous resets are:• ATRESETn• PRESETn• nPORESET.If an implementation retains state in the L1 data cache or L2 cache as described, caremust be taken that reset, particularly nPORESET, does not corrupt the state of theRAM arrays when lowering or raising the power supply to the rest of the processor. Youcan achieve this by clamping the primary I/O to the RAM arrays or designing the RAMarrays in such a way that they do not require a reset. If a reset is required, hardware mustensure that reset is inactive to those RAMs while clamped.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 10-29