Cortex-A8 R2P2.pdf - ARM Information Center

Signal DescriptionsTable A-4 DFT and additional MBIST pin requirements (continued)SignalI/OValue duringfunctional modeValue duringMBIST modeDescriptionTESTEGATE I 0 0 Controls ETM clock gating. Deassert to savepower during MBIST mode.TESTNGATE I 0 0 Controls NEON clock gating. Deassert tosave power during MBIST mode.SE I 0 0 Scan enable signal. Ensures safe shifting ofscan chains.SAFESHIFTRAMIF I 0 0 Prevents the RAM in the instruction fetch unitfrom performing a write operation duringscan shifting.SAFESHIFTRAMLS I 0 0 Prevents the RAM in the load/store unit fromperforming a write operation during scanshifting.SAFESHIFTRAML2 I 0 0 Prevents the RAM in the L2 cache unit fromperforming a write operation during scanshifting.SERIALTEST I 0 0 Concatenates the wrapper boundary registerscan cells into a single scan chain.SHIFTWR I 0 0 IEEE 1500 standard shift signal.CAPTUREWR I 0 0 IEEE 1500 standard capture signal.WINTEST I 0 0 Enables internal testing during ATPG.WEXTEST I 0 0 Enables external testing during ATPG.WSE I 0 0 Wrapper scan enable. Enables serial shiftingof the wrapper scan chain.PRESETn I - 0 Active-LOW APB reset input.ACLKEN I - 1 AXI clock enable signal. This signal must bedriven HIGH for at least one clock cycleduring reset. The value after reset does notaffect the MBIST operation.A-6 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E