Cortex-A8 R2P2.pdf - ARM Information Center

DebugWhen execution of a monitor target starts, the state of the processor is preserved in thesame manner as all ARM exceptions. The monitor target then communicates with thedebugger to access processor and coprocessor state, and to access memory contents andinput/output peripherals. Monitor debug-mode requires a debug monitor program tointerface between the debug hardware and the software debugger.NoteMonitor debug-mode, used for debugging, is not the same as Secure Monitor mode,which is a CPSR[4:0] processor mode.See CP14 c1, Debug Status and Control Register on page 12-21 for information on howto select between Halting debug-mode or Monitor debug-mode.12.2.3 Security extensions and debugTo prevent access to secure system software or data while still permitting Nonsecurestate and optionally secure User mode to be debugged, you can set debug to one of threelevels:• Nonsecure state only• Nonsecure state and Secure User mode only• any Secure or Nonsecure state.The SPIDEN and SPNIDEN signals, and the two bits, SUIDEN and SUNIDEN, in theSecure Debug Enable Register in CP15 coprocessor control the debug permissions. SeeExternal debug interface on page 12-89 and c1, Secure Debug Enable Register onpage 3-71 for details.The processor implements two types of debug support:Invasive debugInvasive debug is defined as a debug process where you can control andobserve the processor. Most debug features in this chapter are consideredinvasive debug because they enable you to halt the processor and modifyits state.SPIDEN and SUIDEN control invasive debug permissions.Noninvasive debugNoninvasive debug is defined as a debug process where you can observethe processor but not control it. The ETM interface and the performancemonitor registers are features of noninvasive debug. See Chapter 14ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 12-5