Cortex-A8 R2P2.pdf - ARM Information Center

Debug12.5.5 Integration Mode Control RegisterThe read/write Integration Mode Control Register enables the processor to switch froma functional mode which is the default, into integration mode, where the inputs andoutputs of the device can be directly controlled for integration testing or topologydetection. When the processor is in this mode, you can use the Integration InternalOutput Control Register or the Integration External Output Control Register to driveoutput values. You can use the Integration Input Status Register to read input values.Figure 12-22 shows the bit arrangement of the Integration Mode Control Register.31 1 0ReservedIntegration mode enableBits Field FunctionFigure 12-22 Integration Mode Control Register formatTable 12-37 shows how the bit values correspond with the Integration Mode ControlRegister functions.[31:1] - Reserved. RAZ, SBZP.Table 12-37 Integration Mode Control Register bit functions[0] Integration mode enable Integration mode enable bit:0 = normal operation, reset value1 = integration mode enabled.When this bit is set to 1, the processor reverts into integration mode to enableintegration testing or topology detection.12.5.6 Claim Tag Set RegisterBits in the Claim Tag Set Register do not have any specific functionality. The externaldebugger and debug monitor set these bits to lay claims on debug resources.Figure 12-23 on page 12-62 shows the bit arrangement of the Claim Tag Set Register.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 12-61