Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorLDR R1, =0x00C00000;MCR p15, 0, R1, c15, c3, 3;MRC p15, 0, R0, c15, c0, 0;Read I-TLB ATTR into data L1 Data 0 RegisterMove I-L1 Data 0 Register to R0TLB PA array examplesTo write one entry in data side TLB PA array, for example:LDR R0, =0x05730000;MCR p15, 0, R0, c15, c0, 0;LDR R1, =0x00C00000;MCR p15, 0, R1, c15, c0, 4;Move R0 to D-L1 Data 0 RegisterWrite D-L1 Data 0 Register to D-TLB PATo read one entry in data side TLB PA array, for example:LDR R1, =0x00C00000;MCR p15, 0, R1, c15, c2, 4;MRC p15, 0, R0, c15, c0, 0;Read D-TLB PA into data L1 Data 0 RegisterMove D-L1 Data 0 Register to R0To write one entry in instruction side TLB PA array, for example:LDR R0, =0x05730000;MCR p15, 0, R0, c15, c1, 0;LDR R1, =0x00C00000;MCR p15, 0, R1, c15, c1, 4;Move R0 to I-L1 Data 0 RegisterWrite I-L1 Data 0 Register to I-TLB PATo read one entry in instruction side TLB PA array, for example:LDR R1, =0x00C00000;MCR p15, 0, R1, c15, c3, 4;MRC p15, 0, R0, c15, c1, 0;Read I-TLB PA into data L1 Data 0 RegisterMove I-L1 Data 0 Register to R03.2.76 c15, L1 HVAB array operationsThe purpose of the L1 HVAB array operations is to:• read the L1 HVAB array contents and write to the system debug data registers• write into the system debug data registers and into the L1 HVAB array.The L1 HVAB array operation is accessible in secure privileged modes only. You cancalculate the value of N in Figure 3-71 on page 3-172 and Figure 3-72 on page 3-172using the NumSets and LineSize fields as defined in Table 3-42 on page 3-56.Figure 3-71 on page 3-172 shows the bit arrangement of the L1 HVAB array readoperation.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 3-171