Cortex-A8 R2P2.pdf - ARM Information Center

List of FiguresCortex-A8 Technical Reference ManualKey to timing diagram conventions .......................................................................... xxxiFigure 1-1 Cortex-A8 block diagram ........................................................................................... 1-4Figure 2-1 32-bit ARM Thumb-2 instruction format .................................................................... 2-4Figure 2-2 ThumbEE Configuration Register format .................................................................. 2-7Figure 2-3 ThumbEE HandlerBase Register format ................................................................... 2-8Figure 2-4 Jazelle Identity Register format ............................................................................... 2-10Figure 2-5 Jazelle Main Configuration Register format ............................................................ 2-11Figure 2-6 Jazelle OS Control Register format ......................................................................... 2-12Figure 2-7 Secure and Nonsecure states ................................................................................. 2-14Figure 2-8 Big-endian addresses of bytes within words ........................................................... 2-19Figure 2-9 Little-endian addresses of bytes within words ......................................................... 2-20Figure 2-10 Register organization in ARM state ......................................................................... 2-25Figure 2-11 Processor register set showing banked registers ................................................... 2-26Figure 2-12 Program status register ........................................................................................... 2-27Figure 3-1 Main ID Register format .......................................................................................... 3-25Figure 3-2 Cache Type Register format ................................................................................... 3-26Figure 3-3 TLB Type Register format ....................................................................................... 3-28Figure 3-4 Processor Feature Register 0 format ...................................................................... 3-30Figure 3-5 Processor Feature Register 1 format ...................................................................... 3-32Figure 3-6 Debug Feature Register 0 format ............................................................................ 3-33Figure 3-7 Memory Model Feature Register 0 format .............................................................. 3-35Figure 3-8 Memory Model Feature Register 1 format .............................................................. 3-37Figure 3-9 Memory Model Feature Register 2 format .............................................................. 3-39ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. xxi