Cortex-A8 R2P2.pdf - ARM Information Center

Programmer’s ModelNoteIf the EmbeddedICE-RT logic is configured into Halting debug-mode, a breakpointinstruction causes the processor to enter debug state. See Halting debug-modedebugging on page 12-4.2.15.12 Exception vectorsThe Secure Configuration Register bits [3:1] determine which mode is entered when anIRQ, a FIQ, or an external abort exception occurs. The CP15 c12, Secure or NonsecureVector Base Address Register and the Monitor Vector Base Address Register define thebase address of the Nonsecure, Secure, and Secure Monitor vector tables. If high vectorsare enabled using CP15 c1 bit[13], the base address of the Nonsecure and Secure vectortables is 0xFFFF0000, regardless of the value of these registers. Enabling high vectors hasno effect on the Secure Monitor vector addresses.2.15.13 Exception prioritiesWhen multiple exceptions arise at the same time, a fixed priority system determines theorder that they are handled. Table 2-13 shows the order of exception priorities.Table 2-13 Exception prioritiesPriorityExceptionHighest 1 Reset2 Precise data abort3 FIQ4 IRQ5 Prefetch abort6 Imprecise data abortLowest 7 BKPTUndefined instructionSVCSMC2-42 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E