Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorTable 3-35 shows how the bit values correspond with the Instruction Set AttributesRegister 4 functions.Table 3-35 Instruction Set Attributes Register 4 bit functionsBits Field Function[31:24] - Reserved, RAZ.[23:20] Exclusiveinstructions[19:16] Barrierinstructions[15:12] SMCinstructions[11:8] Write-backinstructions[7:4] With-shiftinstructions[3:0] UnprivilegedinstructionsIndicates support for exclusive instructions:0x0 = The processor supports CLREX, LDREX{B|H}, and STREX{B|H}.Indicates support for barrier instructions:0x1 = The processor supports DMB, DSB, and ISB.Indicates support for SMC instructions:0x1 = The processor supports SMC.Indicates support for write-back instructions:0x1 = The processor supports all defined write-back addressing modes.Indicates support for with-shift instructions.0x4 = The processor supports:• shifts of loads and stores over the range LSL 0-3• constant shift options• register-controlled shift options.Indicates support for Unprivileged instructions:0x2 = The processor supports LDR{SB|B|SH|H}T.Table 3-36 shows the results of attempted access for each mode.Table 3-36 Results of access to Instruction Set Attributes Register 4 aSecure privileged Nonsecure privileged Secure User Nonsecure UserRead Write Read Write Read Write Read WriteData Undefined Data Undefined Undefined Undefined Undefined Undefineda. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessorinstruction is executed.To access the Instruction Set Attributes Register 4, read CP15 with:MRC p15, 0, , c0, c2, 4 ; Read Instruction Set Attributes Register 4ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 3-51